本論文研製一完整的數位信號輸入D類功率放大系統，在標準元件前端電路與全客戶後端電路兩部份共有四項不同的研究成果。在數位插值濾波器的部分，首先找出最佳效率的升頻濾波方法，爾後找出合適的濾波器架構，並以係數優化演算法獲得硬體效率上的改良。在數位三角積分調變器的部分，本研究提出兩種降低調變輸出信號切換頻率的方法，其一為使用脈波寬度調變器取代原本量化器之優化方案；其二在典型的雜訊移頻迴路中加入濾波元件，以大幅改善脈波密度調變信號固有較高切換頻率之特性，降低輸出頻率將有效減少後端功率放大級之動態功耗。由於第二種調變方法的改良程度更為顯著，用以實現於本論文之晶片內。在後端全客戶電路部分，使用交互電荷泵浦全橋式組態，以n通道功率電晶體作為輸出位準之上拉元件大幅減少晶片面積。其改良後之停滯時間更為充足，而確保圖騰柱電路短路的情況不易發生。

本論文使用TSMC 90-nm CMOS標準製程實現此音頻功率放大之混合信號晶片系統。系統輸入信號為48-kHz取樣之24位元1.002-kHz全擺幅數位弦波，調變器操作頻率為3.072-MHz。在系統頻寬20-kHz下，插值濾波器能提供96-kHz內的鏡像雜訊衰減量大於100-dB，數位三角積分調變器之佈局後邏輯閘層級模擬結果為105.61-dB之SNDR，與657-kHz輸出信號頻率，此輸出信號以數位向量的方式輸入至全客戶電路部分。當負載為8Ω時，設計於晶片外部的被動低通濾波器之差動輸出佈局前模擬結果為0.001759%之THD+N(A-weighted)。經改良的雜訊移頻迴路使全客戶電路的方均根動態功耗由0.58W下降至0.14W。

In this thesis, an entire digital-input class-D power amplifier system is presented. There are four improved results in the whole system, including the front cell-based circuits and the back full-custom circuits. In the part of digital interpolation filter, first, the optimal upsample and filtering scheme is found; second, the appropriate structure for the interpolator is explored; finally, an algorithm of coefficients optimization is proposed to improve the hardware efficiency. In the part of digital delta-sigma modulator (DSM), two approaches are proposed to reduce the toggle rare of modulator output. One is the promoted design of DSM with uniform pulse-width modulation (UPWM) quantizer, the other is adding a unique filter component to the typical noise shaping loop and the inherently high switching rate of the pulse-density modulation (PDM) output is significantly decreased. The lower toggle rate results the lower dynamic power dissipation which is produced by the class-D power stage. The latter noise shaping scheme is more superior than the former scheme, so it is adopted in this amplifier system. In the part of power stage, there are no p-channel power MOSFET in the cross-pumped H-bridge configuration and it results in drasticly reduced chip area. The required dead time of the improved power stage is longer than before, it would ensure the short circuit condition of the power stage totem pole circuits is avoided.
The mixed-signal system-on-chip applied in audio power amplification is fabricated by the TSMC 90-nm CMOS standard process. The part of cell-based circuits is implemented by the TN90GUTM Cell-Based Design Kit. The system input is a 24-bit 1.002-kHz full-scale sinusoid sampled by 48-kHz of sample rate and the digital modulator is sampled by 3.072-MHz. The interpolation filter suppresses the image noise over than 100-dB within 96-kHz and the post-layout gate-level of the modulator output simulation results has an SNDR of 105.61-dB and 657-kHz switching rate within the system bandwidth of 20-kHz. This modulator output is imported to the part of full-custom circuits by digital vector form. The pre-simulated differential output of the out-of-chip passive low-pass filter is 0.001759% THD+N (A-weighted) while a 8Ω load is used. The output of the improved DSM results the RMS (Root-Mean-Square) dynamic power consumption of the part of full-custom circuits from 0.58W reduced to 0.14W.

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