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Author: 葉竣皓
Yeh, Chun-Hao
Thesis Title: 應用於音頻頻帶數位類比轉換器的24位元低成本、高效率插值濾波器和三角積分調變器
24-bit Low-Cost High-Efficiency Interpolation Filter and Delta-Sigma Modulator for Audio-band DACs
Advisor: 郭建宏
Kuo, Chien-Hung
Committee: 黃育賢
Huang, Yu-Hsien
陳建中
Chen, Jiann-Jong
郭建宏
Kuo, Chien-Hung
Approval Date: 2023/07/07
Degree: 碩士
Master
Department: 電機工程學系
Department of Electrical Engineering
Thesis Publication Year: 2023
Academic Year: 111
Language: 中文
Number of pages: 73
Keywords (in Chinese): 數位類比轉換器插值濾波器半頻帶有限脈衝響應濾波器三角積分調變器
Keywords (in English): Digital-to-analog converters, interpolation filters, half-band finite impulse response filters, delta-sigma modulators
DOI URL: http://doi.org/10.6345/NTNU202301449
Thesis Type: Academic thesis/ dissertation
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  • 本論文提出了應用於音頻數位類比轉換器的24位元低成本、高效率插值濾波器和三角積分調變器。在插值濾波器中,我們採用凱薩窗函數來設計具有較少硬體的線性相位半頻帶有限脈衝響應濾波器,除了能有相對較少的濾波器階數外,還能加大頻帶外的阻帶衰減率,並抑制鏡像雜訊。此外,利用多工器來減少大量的加法器,改善使用多相位折疊架構具有加法器數量與濾波器階數成正比的缺點。在三角積分調變器中,使用2+2 SMASH架構來確保高階三角積分調變器的穩定。採用訊號處理電路來節省輸入至第二級電路前的多位元減法器,並於第二級採用硬體成本較低的量化誤差回授架構,改善SMASH架構在硬體成本上的缺點。
      本研究提出的電路架構使用TSMC 0.18-um 1P6M CMOS技術實現,總耗費的核心面積為0.35 mm2。在24 kHz的頻帶下,測得的SNR為143.91 dB,且在1.8 V的電源電壓下,測得功率消耗為3.14 mW。此外,利用Altera Cyclone IV GX型號的FPGA開發板進行驗證,從量測的結果顯示,在24 kHz的頻帶下,測得的效能與post-sim相同。總共使用的邏輯數目(LEs)為3697。在1.2 V的電源電壓下,測得的功率消耗為0.93 mW。

    This paper presents a 24-bit, low-cost, high-efficiency interpolation filter and delta-sigma modulator for audio digital-to-analog converters (DACs). In the interpolation filter, we employ a Kaiser window function to design a linear-phase, half-band finite impulse response (FIR) filter with reduced hardware complexity. This design not only reduces the number of filter stages but also increases the stopband attenuation beyond the passband, effectively suppressing image noise. Additionally, we utilize multiplexers to reduce a large number of adders, addressing the drawback of the polyphaser-folded architecture where the number of adders is proportional to the filter stages. In the delta-sigma modulator, a 2+2 SMASH architecture is used to ensure stability for higher-order delta-sigma modulator. Signal processing circuits are employed to save multi-bit subtractors before the second stage, and a error feedback structure with lower hardware cost is implemented in the second stage to address the hardware cost limitation of the SMASH architecture.
      The proposed architecture in this study was implemented using TSMC 0.18-um 1P6M CMOS technology, with a total core area of 0.35 mm2. In the 24 kHz bandwidth, the measured SNR was 143.91 dB, and the power consumption was measured at 3.14 mW with a supply voltage of 1.8 V. Furthermore, verification was performed using an Altera Cyclone IV GX model FPGA development board, and the measured performance in the 24 kHz bandwidth matched the post-simulation results. The total number of used logic elements (LEs) was 3697. At a supply voltage of 1.2 V, the measured power consumption was 0.93 mW.

    謝   辭 i 摘   要 iii ABSTRACT iv 目   錄 vi 表 目 錄 ix 圖 目 錄 x 第一章 緒論 1 1.1 研究動機與背景 1 1.2 數位電路設計流程 2 1.3 論文架構與研究方法 4 第二章 插值濾波器和三角積分調變器概論 5 2.1 量化器 5 2.1.1 單一位元量化器 6 2.2.2 多位元量化器 7 2.2.3 量化誤差 9 2.2 效能指標 10 2.2.1 訊號雜訊比 10 2.2.2 訊號雜訊失真比 11 2.2.3 有效位元數 11 2.2.4 無雜訊干擾之動態範圍 12 2.2.5 總諧波失真 12 2.2.6 總諧波失真加雜訊 12 2.2.7 動態範圍 13 2.2.8 截止帶衰減率 13 2.2.9 通帶漣波 14 2.2.10 過渡帶 15 2.3 插值濾波器概論 15 2.3.1 離散時間訊號 15 2.3.2 升頻方法 16 2.3.2.1 保持暫存上取樣 16 2.3.2.2 零值插入上取樣 17 2.4 三角積分調變器概論 18 2.4.1 超取樣技術 18 2.4.2 雜訊移頻技術 20 2.4.3 低階三角積分調變器 22 2.4.4 二階三角積分調變器 25 2.4.4.1  分散式回授串聯積分器(CIFB)架構 26 2.4.4.2  分散式前饋串聯積分器(CIFF)架構 28 2.4.5  高階三角積分調變器 28 2.4.5.1  分散式回授串聯共振器(CRFB)架構 30 2.4.5.2  量化誤差回授(EF)架構 30 2.4.5.3  多級迴路(MASH)架構 32 2.4.5.4  堅固式多級雜訊移頻(SMASH)架構 33 第三章 數位插值濾波器 35 3.1 插值濾波器 35 3.1.1 多級架構 36 3.1.2 濾波器規格 39 3.1.3 濾波器種類 40 3.1.4 有限脈衝響應濾波器 41 3.1.4.1 多相位半頻帶有限脈衝響應濾波器 42 3.2 濾波器窗函數 44 3.2.1 凱薩窗函數 44 3.3 提出的插值濾波器架構 46 3.4 插值濾波器的優化實現架構 47 第四章 數位三角積分調變器 52 4.1 數位三角積分調變器之架構考量 52 4.1.1 2+2堅固式多級雜訊移頻架構 52 4.1.2 提出的2+2堅固式多級雜訊移頻架構 53 4.1.2.1 架構係數 54 4.1.2.2 訊號處理電路 57 4.2 整體電路模擬結果 58 第五章 積體電路的實現與量測結果 60 5.1 提出架構的自動佈局與繞線 60 5.1.1 自動佈局與繞線 60 5.1.2 I/O Pad的擺放 61 5.1.3 Post-layout gate-level的模擬結果 62 5.2 提出架構的FPGA開發板實現 63 第六章 論文總結和未來展望 65 6.1 論文總結 65 6.2 未來展望 67 參 考 文 獻 69 自    傳 72

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