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研究生: 潘偉正
Pan, Wei-Zheng
論文名稱: SIFT影像辨識演算法及其在FPGA之實現
FPGA-Based Implementation for Scale Invariant Feature Transform (SIFT) of Image Recognition Algorithm
指導教授: 許陳鑑
Hsu, Chen-Chien
王偉彥
Wang, Wei-Yen
學位類別: 碩士
Master
系所名稱: 電機工程學系
Department of Electrical Engineering
論文出版年: 2016
畢業學年度: 104
語文別: 中文
論文頁數: 115
中文關鍵詞: 影像辨識影像特徵提取SIFT演算法FPGA
英文關鍵詞: Image recognition, Image keypoint extracting, SIFT algorithm, FPGA
DOI URL: https://doi.org/10.6345/NTNU202204556
論文種類: 學術論文
相關次數: 點閱:176下載:25
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  • 本文提出將SIFT影像辨識演算法實現於FPGA上,以解決影像辨識需要大量運算時間,而使得系統無法即時運算之問題。為了大幅減少邏輯單元之需求以及提升系統頻率,我們依照硬體適合之架構以及平行處理的優勢,針對SIFT演算法進行改良,如使用軟體預先計算高斯模板、使用數值方式避免反矩陣使用除法器以及將影像金字塔使用平行處理之架構實現等。除此之外,我們也使用CORDIC演算法進行三角函數、平方相加開根號以及反三角函數等實現,還有使用最佳化演算法找出高斯影像所需之最佳參數,並在硬體中進行連續高斯影像金字塔之近似,最後使用硬體實現影像梯度直方圖統計,如此一來就能於硬體中進行特徵主方向偵測以及特徵點描述之功能,而論文中會清楚介紹上述所提到之實現方法。而為了降低開發之困難性,首先以軟硬協同設計之架構對部分模組進行加速設計,完成後,再將整個系統以全硬體方式進行實現,值得一提的是,整個系統電路皆是由管線架構設計而成,因此可以大幅提升運算效率,進而達到即時運算之目標,從實驗結果證實,電路模組運算速度相較於軟體有大幅提升,而硬體實現結果相較於軟體之誤差也保有相當之精確度。

    To solve the problem of image recognition, which requires plenty of computation time by software, we present a hardware implementation approach of SIFT recognition algorithm to achieve the goal of real time execution, through the use of offline calculation of the Gaussian kernel by software, a mathematical derivation to calculate inverse matrix without using any divisors, realization of image pyramid in parallel, etc. As a result, the system performs well in reducing a number of logic units required and the system frequency is significantly increased. In addition, the CORDIC algorithm is employed to implement not only mathematical functions such as trigonometric functions and square root computation, but also an image gradient histogram successfully by hardware. Consequently, the dominant orientation detection and key point descriptors can be implemented by image gradient histogram. To develop an applicable system, the first step is to apply the software and hardware co-design approach to accelerate functional modules and subsequenty implement the entire system in pure hardware. Besides, the structure of all modules is based on pipeline design. Experimental results demonstrated that the proposed approach has significantly reduced computation time required and efficiently increased maximum system frequency. Most importantly, the execution speed has achieved real time computation for practical applications.

    摘   要 i ABSTRACT ii 致   謝 iii 目   錄 iv 表 目 錄 viii 圖 目 錄 xii 第一章 緒論 1 1.1 研究背景與動機 1 1.2 論文架構 5 第二章 演算法回顧 6 2.1 SIFT演算法介紹 6 2.1.1 影像金字塔 6 2.1.2 特徵點偵測 8 2.1.3 特徵點主方向 13 2.1.4 特徵點描述 15 2.1.5 特徵點匹配 17 2.2 CORDIC介紹 18 第三章 SIFT演算法實現於硬體之改良 26 3.1 改良高斯影像之實現 26 3.2 改良影像金字塔之實現 27 3.3 消除低對比度特徵點 41 第四章 實驗平台介紹 44 4.1 硬體實驗平台介紹 44 4.1.1 DE2-70 多媒體開發板 45 4.1.2 D5M影像擷取模組 47 4.2 軟體實驗平台介紹 48 4.2.1 PC軟體實驗平台 48 4.2.2 NIOS II軟體實驗平台 49 第五章 SIFT硬體加速模組 50 5.1 系統硬體架構 50 5.2 Image Encode模組 52 5.3 Image Buffer模組 53 5.4 Image Pyramid模組 54 5.4.1 Gaussian Pyramid 55 5.4.2 DOG Pyramid 55 5.4.3 DOG Image模組 56 5.5 Gaussian Filter模組 57 5.5.1 MAC模組 58 5.5.2 Parallel Adder模組 59 5.6 Down Sample模組 60 5.7 Window模組 61 5.8 SIFT Detection模組 62 5.8.1 Extrema Detection模組 64 5.8.2 Unstable Point Detection模組 67 5.8.3 Maximum Detection模組 68 5.8.4 Max Value Test 模組 70 5.8.5 Extrema Test模組 71 5.8.6 Minimum Detection模組 72 5.8.7 Min Value Test模組 73 5.8.8 Differential Matrix模組 74 5.8.9 Hessian Matrix模組 75 5.8.10 Inverse Hessian matrix模組 78 5.8.11 Edge Detection模組 79 5.8.12 Low Contrast Detection模組 81 5.9 Dominant Orientation Detection模組 82 5.9.1 Image Gradient模組 84 5.9.2 CORDIC_Sin_Cos模組 85 5.9.3 CORDIC_Sqrt_Atan模組 86 5.9.4 DCFIFO_Controller模組 87 5.9.5 Orientation_DCFIFO模組 88 5.9.6 Initial Counter模組 89 5.9.7 StatisticsOrientationMagnitude模組 89 5.9.8 StatisticsOrientationMUX模組 90 5.9.9 Maximum Orientation Detection模組 91 第六章 模擬與實驗結果 94 6.1 SIFT軟體模擬結果 94 6.2 SIFT軟硬體效能之比較 97 6.2.1 高斯影像軟硬體比較: 97 6.2.2 影像金字塔 99 6.2.3 Low Contrast Detection模組比較 101 6.2.4 SIFT Detection 102 6.2.5 CORDIC軟硬體結果比較 104 6.2.6 模組資料 107 第七章 結論 108 7.1 結論 108 7.2 未來展望 109 參考文獻 110 自 傳 113 學術成就 115

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