元件尺寸微縮在相同的面積下有著更高的效能，因此元件大小成 為現今科技業一直持續努力的目標，然而隨著元件尺寸持續的微縮， 短通道效應也隨著元件的微縮到來，當通道到達了數十奈米甚至是奈 米量級的時候，嚴重的短通道效應將會帶來許多問題，因此能夠有效 控制閘極能力至關重要，目前發展出許多方法來改善短通道效應，通 道使用奈米線並配合三維結構如鰭式電晶體、Ω 形電晶體，藉由增加 閘極的控制面積，來有效抑制漏電流，而這類型的電晶體也是在物聯 網時代低耗能的候選者。
本論文主要探討的是透過台灣半導體實驗室(TSRI) 0.35μm 製程 的設備，製作 Ω 型金氧半場效電晶體(Ω-Shape MOSFETs)和 Ω 型 無接面式電晶體(Ω-Shape JLFETs)，藉由在矽基板上堆疊二氧化矽 和多晶矽來取代 SOI，盡可能降低成本並配合 365 奈米 I-Line 光學 步進機快速生產元件，配合各種方式來微縮元件尺寸，藉此開發具有 奈米級線寬的電晶體。

In order to improve CMOS device performance, we expect place more transistors on a single chip, so the shrinking of transistors is necessary. However, the short channel effects (SCE) are followed with transistors scaling down to nano-scaled. The 3D transistors such as FinFETs Ω-FET or nanowire have superior gate controllability to suppress SCE which are candidates for low-power application in the IoT (internet of things) era.
In this work, we fabricate Ω-Shape enhancement mode FET (Ω-Shape FET) and Ω-Shape Junctionless FET (Ω-Shape JLFET) by Taiwan Semiconductor Research Institute (TSRI) 0.35μm process line. Stacking SiO2 and Poly-Si on the Si substrate to replace SOI wafer has an advantage of cost reduction. On the other hand, 365nm I-Line stepper could meet the requirement of rapid production. Therefore, we can develop any different size nano-scaled 3D transistor.

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