伴隨著技術節點的演進有助於人工智慧與物聯網的快速發展，電子元件須滿足低功耗、高密度、高效能等特性，目前已經能透過鰭式電晶體、環繞式閘極電晶體等多閘極三維電晶體，有效增加閘極控制通道的能力以至於降低漏電流並且解決尺寸微縮所導致的短通道效應，進而使續摩爾定律(Moore’s Law)延續。近年來鐵電材料於記憶體領域得到廣泛的研究，由於鉿基氧化物的鐵電材料具有與CMOS製程優異的相容性，相比傳統鈣鈦礦的鐵電材料成為新興記憶體的候選者之一。
本論文研究分為三個部分，第一部份透過台灣半導體中心提供的i-line(365 nm)機台開發出鰭式電晶體，第二部分透過原子層沉積系統調變不同前驅物沉積順序，分別開發奈米貼合與超晶格之鐵電氧化鉿鋯堆疊製程，由於奈米貼合(Nano-laminated)與超晶格(Superlattice)的結構有助於鐵電氧化層的結晶，進階將它們應用於三維的鰭式場效電晶體。第三部分為開發三維垂直式陣列鐵電穿隧接面架構的製程。
本論文成功演示分別將奈米貼合、超晶格與鐵電穿隧接面元件應用於三維的鰭式場效電晶體與三維垂直式陣列記憶體結構，並且超晶格的結果顯示在尺寸微縮下同時保持優異的鐵電記憶體特性，而三維垂直結構的鐵電穿隧接面元件透過調變電壓使電流比明顯上升。本論文之結果有助於未來發展3D NAND的架構。

In order to meet the requirement of future technology nodes for artificial intelligence (AI) and the Internet of Things (IoT), the high performance, high-density and low power consumption are highly demanded. The non-planar FET, such as FinFET and GAAFET, has been proposed to improve the gate control capability for reducing leakage current and suppressing short channel effect with device scaling down under continuing the Moore's Law. Recently, hafnium oxide-based ferroelectric (FE) materials have been extensively investigated in the memory due to process compatibility with CMOS. It has the advantage as compare to traditional perovskite materials and as candidates for emerging memory applications.
There are three parts in this thesis. One is i-line-based (365 nm) FinFET process by Taiwan Semiconductor Research Institute (TSRI). The second part is ferroelectric HfZrO2 (HZO) stacking combination with the nano-laminated (NL) or superlattice (SL) by atomic layer deposition (ALD) system. The ferroelectric characteristics would be improved with NL and SL structures, and applied to 3D FinFET. The third part is 3D vertical array ferroelectric tunnel junction (FTJ) memory architecture.
The nano-laminated and superlattice for 3D FinFET, and 3D vertical FTJ array memory are successfully demonstrated. The superlattice HZO exhibits the superior memory characteristic with device scaling down. The current ratio of the 3D vertical FTJ structure increases significantly with increasing the applied voltage. Overall the conclusion of this thesis benefits for the 3D NAND memory architecture in the future.

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