現今元件閘極線寬越做越小，所需電流大小要求約來越高，控能力也相對增加，為了滿足這些需求，現今二氧化矽當作閘極氧化層半導體，已不符現今半導體界的使用，因為閘極氧化層屬用傳統的二氧化矽絕緣層厚度將需要縮小到約奈米等級，要維持在電性操作時之等效氧化層厚度 不變，在文獻中，以研究取代二氧化矽的新材料，在閘極厚度減少，但是還有電容值可以存取，不會因為閘極太薄，造成閘極漏電的機制與避免穿隧效應的產生。所以使用高介電常數 ( high-k ) 的材料及使用金屬閘極來取代二氧化矽是必需的。於是使用高介電常數材料作為絕緣層，同時閘極絕緣層實際厚度與電性等效厚度便成現今所需解決的問題；另外使用矽鍺材料改善元件特性。對於奈米尺寸元件，鍺具有較大遷移率增加，在不同的通道載子傳輸方向及基板方位下，了解遷移率的理論。
本次實驗結果可知，在透過製程及退火條件之下，均可得到不錯的HfSiOx薄膜與金屬TiN品質及其電性表現，尤其在微縮等效氧化層厚度及抑制漏電流方面的優點。

Today, as MOSFET’s gate length getting small, to increase driving current and enhance gate control capability. in order to satisfy these requirements , It isn't comform to the semiconductor nowadays that SiO2 uses for gate oxide. Because the thickness of the insulator SiO2 will need to be reduced to small nanometer length, while keeping the EOT (equivalent oxide thickness) to maintain the characteristics of the devices. In the paper, in nanometer technology node, however, the electrons of the gate can flow through gate oxide into drain by tunneling in this place , and produce large leakage current . Using a new material with a dielectric constant greater than that of SiO2 to replace SiO2 film as gate dielectrics is an indispensable task.. Using insulators with high dielectric constant is one of the attractive and popular method to research the problem. Besides, SiGe materials has an important technique for improving the device performance other than conventional scaling method. Germanium can provide large mobility enhancement for CMOS. It will be of great importance to know the theoretical limit of mobility under various channel direction, and substrate orientation for device.
In this research, we use the anneal process and fabrication that get good quality of HfSiOx film and metal TiN. There are suppression of leakage current and reduce of oxide layer for the device.

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