隨著元件微縮達到物理極限，鐵電負電容這項概念將是一個能突破現況的轉捩點，目前此領域不管是UC Berkeley的S. Salahuddin教授或Fraunhofer Center的Johannes Müller等專家都已推廣鐵電負電容概念。
室溫下的MOSFET之Boltzmann tyranny物理極限2.3kbT/decade限制了開關特性斜率，堆疊鐵電層(FE) 作為具有負電容(NC)效應之介電層提供低開啟電壓(< 0.2 V)像穿戴式裝置、生物醫學電子與物聯網(IoT)應用之可行辦法，為了驗證NC的概念可將body factor (m)<1，利用Landau model模擬NC效應並建立其理論模型。然而，負電容效應中最具代表性的電滯迴圈會因鐵電層厚度而產生電滯現象，此現象對於製作記憶體很重要；但是為了應用在CMOS操作上，電滯現象就會成為元件性能上缺點，所以需要找到能不產生電滯現象且具有最小次臨界擺幅(SS)的最佳鐵電層厚度才能達到陡峭斜率電晶體。鐵電負電容目前被廣泛運用成NCFET並證實其有效性，而為了使電性臻於完美，傳輸機制(n factor)也是另外一項可改善的參數，搭配ultra-thin body與double gate成為UTB-DG-NCFET能使SS明顯下降，最後再結合tunneling FET三種加強效果下誕生了能在 0.2V內完全開啟的UTB-DG-NCTFET，此元件達到了未來sub-10nm技術的低電壓(Low voltage)之超陡峭斜率 (Super-Steep slope)次世代電晶體研究。

The concept of ferroelectric negative capacitance could be a turning point to break through the state-of-the-art with scaling-down to reach physical limitation. Currently, authority in this field whether Prof. S. Salahuddin in UC Berkeley's or Johannes Müller in Fraunhofer Center and other experts have promoted the concept of a ferroelectric negative capacitance for a period of time.
Physical limitation of Boltzmann tyranny with 2.3kbT/decade for MOSFET at room temperature restricts the switching slope. Integrated ferroelectric (FE) as dielectric with negative capacitance (NC) effect provides a feasible and synergistic solution for low-power < 0.2 V operation such as wearable devices, bioelectronics, and IoT applications. To demonstrate the concept of negative capacitance(body factor (m) <1), the simulation of NC Effects were used by Landau model to build the theoretical model. However, hysteresis loop would cause phenomenon of hysteresis by thickness of ferroelectric layer. The effect of hyseresis is very important to memory fabrication. In order to applicate CMOS, this effect will be a defect in the devices’ performance. So we should find the optimized thickness of ferroelectric layer with hysteresis-free and lowest SS to achieve steep slope transistor. Ferroelectric negative capacitance have been widely used and proven its validity for NCFET. For reaching ideal state, transport mechanism (n factor) is another parameter to improve. With ultra-thin body, double gate and tunneling FET, it bring out UTB-DG-NCTFET in sub-0.2V operation to achieve low voltage super-steep slope transistors in the development of sub-10nm technology.

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