為達到人工智能（AI）之物聯網（IoT）及高速傳輸之5G/6G科技，高密度的記憶體內/近運算高度需求。近年來各方領域的近記憶體運算與記憶體內建邏輯紛紛被提出，利用各種新興非揮發性記憶體(Emerging non-volatile memory, e-NVM) ，以實現內部存取並執行邏輯操作減少耗時與耗能的問題。本論文便是討論鐵電電晶體之類比式操作與後段製程相容之設計。
研究中採用直流 (DC) 掃描、脈衝測量、Endurance和Retention的方法來研究元件特性。因此，第二章會介紹實驗的測量設備和波形設置。
在第三章中，驗證雙 HZO 鐵電場效應電晶體 (FeFET) 可多階操作 (MLC)以 提高NVM密度。與單HZO FeFET 相比，金屬層/鐵電層/金屬層/鐵電層/矽基板 (MFMFS) FeFET 能夠在 ±3 V 的超低寫入/抹除電壓 (VP/E) 下實現2-bit位操作，並具有穩定的數據保持能力>104秒和>107次循環的耐用性。此外，通過使用金屬層/鐵電層/介電層/鐵電層/矽基板結構將記憶窗戶(MW)擴大至2.6 V，讀取錯誤率(ER)比單HZO低600倍。兩種雙HZO FeFET都通過使用電壓調整的方案展示具有高度線性和對稱性的深度學習能力。
在第四章中，完成具有>106高開關電流比(Ion/Ioff)和4cm2/V⸳s 遷移率的無退火 In2O3 薄膜電晶體 (TFT)，採用20sccm的Ar和15 W的濺射系統沉積。最後將鐵電電容與In2O3-TFT串聯，成功觀察到磁滯特性，並完成FE電容與In2O3-TFT的面積比對磁滯差異進行實驗驗證。因此，In2O3-TFT 有望在未來與鐵電記憶體整合，用於後端製程 (BEOL)。

In order to achieve internet of thing (IoT) for artificial intelligence (AI) and high-speed communication with 5G/6G, the high-density in/near-memory-computing is urgently demanded. Recently, the in/near-memory-computing for kinds of Emerging non-volatile memory (eNVM) were proposed to reduce power consumption and time. In this thesis, the design of ferroelectric Field-Effect-Transistor (FeFET) for analog operation and Back end of line (BEOL) compatible process will be investigated.
In Chapter 2, the measurement tools and technique will be introduced, such as direct current (DC) sweep, pulse measurement, endurance, and retention, as well as waveform setup for following experiment.
In chapter 3, the double-HZO ferroelectric field-effect transistors (FeFETs) exhibits multilevel cell (MLC) to enhance NVM density. As compare to single-HZO FeFETs, metal/ferroelectric/metal/ferroelectric/Si (MFMFS) FeFETs has achieved 2-bit operation under ultra-low program/erase voltage (VP/E) of ±3 V with stable data retention of >104 s and robust endurance of 107 cycles. In addition, the enhancement of memory window (MW) with 2.6 V by using metal/ferroelectric/insulator/ferroelectric/Si leads to 600x lower error rate (ER) than single-HZO. Both double-HZO FeFETs demonstrated the capability of deep neural network (DNN) with nonlinearity and symmetry synaptic operation by using amplitude modulation scheme.
In chapter 4, In2¬O¬3 thin film transistors (TFTs) with annealing-free exhibits high on/off-state current ratio of >106 with mobility of 4 cm2/V⸳s.¬, which fabricated by sputtering system with 20 sccm of Ar and 15 W. The proposed In2O3-TFT connected with ferroelectric capacitor in series to validate hysteretic characteristics. The Vt related to the area ratio of FE capacitor and In2O3-TFT. The In2O3-TFT is promising to integrated for ferroelectric memory toward back end of line (BEOL) in the future.

[1] A. Sebastian, "In-memory computing for AI," Short Course, 2019 IEDM, Dec. 8 2019
[2] K.-Y. Hsiang et al., "Ferroelectric HfZrO2 with electrode engineering and stimulation schemes as symmetric analog synaptic weight element for deep neural network training," IEEE Transactions on Electron Devices, vol. 67, no. 10, pp. 4201-4207, 2020.
[3] P. Machanick, "Approaches to addressing the memory wall," School of IT and Electrical Engineering, University of Queensland, 2002.
[4] A. Sebastian, "Ferroelectricity in Materials and Device Applications," Short Course, 2022 VLSI-TSA, April 18. 8 2022
[5] G. Sun et al., "Memory that never forgets: emerging nonvolatile memory and the implication for architecture design," National Science Review, vol. 5, no. 4, pp. 577-592, 2018.
[6] M. H. Park et al., "Review and perspective on ferroelectric HfO2-based thin films for memory applications," MRS Communications, vol. 8, no. 3, pp. 795-808, 2018.
[7] J. Muller et al., "Ferroelectricity in simple binary ZrO2 and HfO2," Nano letters, vol. 12, no. 8, pp. 4318-4323, 2012.
[8] B1500A Semiconductor Device Analyzer user’s manual,pp.1,4-2,32.
[9] Agilent B Pulsed-IV Parametric Test Solutions,pp5-13
[10] J. Müller, T.S. Böscke, S. Müller, E. Yurchuk, P. Polakowski, J. Paul, D. Martin, T. Schenk, K. Khullar, A. Kersch, W. Weinreich, S. Riedel, K. Seidel, A. Kumar, T.M. Arruda, S.V. Kalinin, T. Schlösser, R. Boschke, R. van Bentum, U. Schröder, and T. Mikolajick, “ Ferroelectric Hafnium Oxide: A CMOS-compatible and highly scalable approach to future ferroelectric memories, ” in IEDM Tech. Dig., Dec. 2013, pp. 280-283.
[11] M. H. Lee, P.-G. Chen, C. Liu, K-Y. Chu, C.-C. Cheng, M.-J. Xie, S.-N. Liu, J.-W. Lee, S.-J. Huang, M.-H. Liao, M. Tang, K.-S. Li and M.-C. Chen, “Prospects for Ferroelectric HfZrOx FETs with Experimentally CET=0.98nm, SSfor=42mV/dec, SSrev=28mV/dec, Switch-OFF <0.2V, and Hysteresis-Free Strategies, ” Technical Digest, International Electron Device Meeting (IEDM), Washington D.C., pp. 616-619, Dec. 7-9, 2015.
[12] M. H. Park, H. J. Kim, Y. J. Kim, T. Moon, K. D. Kim, and C. S. Hwang, “Toward a multifunctional monolithic device based on pyroelectricity and the electrocaloric effect of thin antiferroelectric HfXZr1−XO2 films, ” Nano Energy, vol. 12, pp. 131-140, Mar. 2015.
[13] R. Eskandari, X. Zhang, and L. M. Malkinski, “Polarization-dependent photovoltaic effect in ferroelectric-semiconductor system, ” Appl. Phys. Lett., vol. 110, 121105, 2017.
[14] M. H. Lee, K.-T. Chen, C.-Y. Liao, G.-Y. Siang, C. Lo, H.-Y. Chen, Y.-J. Tseng, C.-Y. Chueh, C. Chang, Y.-Y. Lin, Y.-J. Yang, F.-C. Hsieh, S. T. Chang, M.-H. Liao, K.-S. Li, and C. W. Liu, “Bi-directional Sub-60mV/dec, Hysteresis-Free, Reducing Onset Voltage and High Speed Response of Ferroelectric-AntiFerroelectric Hf0.25Zr0.75O2 Negative Capacitance FETs, ” in IEDM Tech. Dig., Dec. 2019, pp. 566-569.
[15] M. H. Lee, K.-T. Chen, C.-Y. Liao, S.-S. Gu, G.-Y. Siang, Y.-C. Chou, H.-Y. Chen, J. Le, R.-C. Hong, Z.-Y. Wang, S.-Y. Chen, P.-G. Chen, M. Tang, Y.-D. Lin, H.-Y. Lee, K.-S. Li, and C. W. Liu, “Extremely Steep Switch of Negative-Capacitance Nanosheet GAA-FETs and FinFETs, ” Technical Digest, International Electron Device Meeting (IEDM), pp. 735-738, San Francisco, Dec. 1-5, 2018.
[16] K. Chatterjee, S. Kim, G. Karbasian, A. J. Tan, A. K. Yadav, A. I. Khan, C. Hu, and S. Salahuddin, “Self-Aligned, Gate Last, FDSOI, Ferroelectric Gate Memory Device With 5.5-nm Hf0.8Zr0.2O2, High Endurance and Breakdown Recovery, ” IEEE Electron Device Letter, vol. 38, no. 10, pp. 1379-1382, Oct. 2017.
[17] S. Dünkel, M. Trentzsch, R. Richter, P. Moll, C. Fuchs, O. Gehring, M. Majer, S. Wittek, B. Müller, T. Melde, H. Mulaosmanovic, S. Slesazeck, S. Müller, J. Ocker, M. Noack, D.-A. Löhr, P. Polakowski, J. Müller, T. Mikolajick, J. Höntschel, B. Rice, J. Pellerin, and S. Beyer, “A FeFET based super-low-power ultra-fast embedded NVM technology for 22nm FDSOI and beyond, ” IEDM, pp. 485-488, 2017.
[18] M. Trentzsch, S. Flachowsky, R. Richter, J. Paul, B. Reimer, D. Utess, S. Jansen, H. Mulaosmanovic, S. Müller, S. Slesazeck, J. Ocker, M. Noack, J. Müller, P. Polakowski, J. Schreiter, S. Beyer, T. Mikolajick, and B. Rice, “A 28nm HKMG super low power embedded NVM technology based on ferroelectric FETs, ” IEDM, pp. 294-297, 2016.
[19] R. Cao, Y. Wang, S. Zhao, Y. Yang, X. Zhao, W. Wang, X. Zhang , H. Lv, Q. Liu, and M. Liu, “Effects of Capping Electrode on Ferroelectric Properties of Hf0.5Zr0.5O2 Thin Films, ” IEEE Electron Device Letter, vol. 39, no. 8, pp. 1207-1210, Aug. 2018.
 
[20] K. T. Chen, C. Y. Liao, C. Lo, H. Y. Chen, G. Y. Siang, S. Liu, S. C. Chang, M. H. Liao, S. T. Chang, and M. H. Lee*, “Improvement on Ferroelectricity and Endurance of Ultra-Thin HfZrO2 Capacitor with Molybdenum Capping Electrode, ” The 3rd Electron Devices Technology and Manufacturing (EDTM), Mat 1: Ferroelectric Materials and Devices, Singapore, Mar. 13-15, 2019.
[21] H. J. Kim, M. H. Park, Y. J. Kim, Y. H. Lee, W. Jeon, T. Gwon, T. Moon, K. D. Kim, and C. S. Hwang, “Grain size engineering for ferroelectric Hf0.5Zr0.5O2 films by an insertion of Al2O3 interlayer, ” Appl. Phys. Lett., 105, 192903, Nov. 2014.
[22] M. H. Park, H. J. Kim, Y. J. Kim, T. Moon, and C. S. Hwang, “The effects of crystallographic orientation and strain of thin Hf0.5Zr0.5O2 film on its ferroelectricity, ” Appl. Phys. Lett., 104, 072901, Feb. 2014.
[23] T. Kim, J. A. del Alamo and D. A. Antoniadis, “Dynamics of HfZrO2 Ferroelectric Structures: Experiments and Models, ” in IEDM Tech. Dig., Dec. 2020, pp. 441-444.
[24] Kai Ni1 , Jeffrey Smith1 , Huacheng Ye1 , Benjamin Grisafe1 , G. Bruce Rayner3 , Andrew Kummel2, “ A Novel Ferroelectric Superlattice Based Multi-Level Cell Non-Volatile Memory ”, IEDM19-669, ©2019 IEEE
[25] C.-Y. Liao, K.-Y. Hsiang, F.-C. Hsieh, S.-H. Chiang, S.-H. Chang, J.-H. Liu, C.-F. Lou, C.-Y. Lin, T.-C. Chen, C.-S. Chang, and M. H. Lee, “Multibit Ferroelectric FET Based on Nonidentical Double HfZrO2 for High-Density Nonvolatile Memory,” IEEE Electron Device Letter, 2021.
[26] M. Jerry, P.-Y. Chen, J. Zhang, P. Sharma, K. Ni, S. Yu, S. Datta, “Ferroelectric FET analog synapse for acceleration of deep neural network training, ” in IEDM Tech. Dig., Dec. 2017, pp. 139-142.
[27] K.-Y. Hsiang, C.-Y. Liao, K.-T. Chen, Y.-Y. Lin, C.-Y. Chueh, C. Chang, Y.-J. Tseng, Y.-J. Yang, M.-H. Liao, T.-H. Hou, C.-H. Wu, C.-C. Ho, J.-P. Chiu, C.-S. Chang, M. H. Lee , “Ferroelectric HfZrO2 With Electrode Engineering and Stimulation Schemes as Symmetric Analog Synaptic Weight Element for Deep Neural Network Training” in TED OCTOBER 2020, VOL. 67, NO. 10.
[28] Z.-F. Lou, C.-Y. Liao, K.-Y. Hsiang, C.-Y. Lin, Y.-D. Lin, P.-C. Yeh, C.-Y. Wang, H.-Y. Yang, P.-J. Tzeng, T.-H. Hou, Y.-T. Tang, M. H. Lee, “Characterization of double HfZrO2 based FeFET toward low-voltage multi-level operation for high density nonvolatile memory,” in 2022 VLSI-TSA, Hsinchu, Taiwan, Apr. 18‒21, 2022, pp. 1‒2.
[29] Vita P.-H. Hu, H.-H. Lin, Z.-A. Zheng, Z.-T. Lin, Y.-C. Lu, T.-Y. Ho, Y.-W. Lee, C.-W. Su and C.-J. Su, "Split-Gate FeFET (SG-FeFET) with Dynamic Memory Window Modulation for NonVolatile Memory and Neuromorphic Applications," Symposium on VLSI Technology, 2019, pp. T134-T135.
[30] Vita P.-H. Hu, H.-H. Lin, Z.-A. Zheng, Z.-T. Lin, Y.-C. Lu, T.-Y. Ho, Y.-W. Lee, C.-W. Su and C.-J. Su, "Split-Gate FeFET (SG-FeFET) with Dynamic Memory Window Modulation for NonVolatile Memory and Neuromorphic Applications," Symposium on VLSI Technology, 2019, pp. T134-T135.
[31] S. Datta, S. Dutta, B. Grisafe, J. Smith, S. Srinivasa, and H. Ye, “Back-end-of-line compatible transistors for monolithic 3-D integration,” IEEE Micro, vol. 39, no. 6, pp. 8-15, Nov. 2019, doi: 10.1109/MM.2019.2942978.
[32] E. P. Denton, H. Rawson, and J. E Stanworth, “Vanadate glasses,” Nature, vol. 173, pp. 1030-1032, May 1954, doi: 10.1038/1731030b0.
[33] H. Hosono, “Ionic amorphous oxide semiconductors: material design, carrier transport, and device application,” Journal of Non-Crystalline Solids, vol. 352, pp. 851-858, Apr. 2006, doi: 10.1016/j.jnoncrysol.2006.01.073.
[34] M. Si, Z. Lin, Z. Chen, and P. D. Ye, “First demonstration of atomic-layer-deposited BEOL-compatible In2O3 3D Fin transistors and integrated circuit: high mobility of 113 cm2/V∙s, maximum drain current of 2.5 mA/μm and maximum voltage gain of 38 V/V in In2O3 inverter,” in VLSI symp., June 2021, T2-4.
[35] M. Trentzsch, S. Flachowsky, R. Richter, J. Paul, B. Reimer, D. Utess, S. Jansen, H. Mulaosmanovic, S. Müller, S. Slesazeck, J. Ocker, M. Noack, J. Müller, P. Polakowski, J. Schreiter, S. Beyer, T. Mikolajick, and B. Rice, “A 28 nm HKMG super low power embedded NVM technology based on ferroelectric FETs,” in IEDM Tech. Dig., Dec. 2016, pp. 294–297, doi: 10.1109/IEDM.2016.7838397.
[36] K.-T. Chen, H.-Y. Chen, C.-Y. Liao, G.-Y. Siang, C. Lo, M.-H. Liao, K.-S. Li, S. T. Chang, and M. H. Lee, “Non-volatile ferroelectric FETs using 5-nm Hf0.5Zr0.5O2 with high data retention and read endurance for 1T memory applications,” IEEE Electron Device Letters, vol. 40, no. 3, pp. 399–402, Mar. 2019, doi: 10.1109/LED.2019.2896231.
[37] Z. Liang, K. Tang, J. Dong, Q. Li, Y. Zhou, R. Zhu, Y. Wu, D. Han, and R. Huang, “A novel high-endurance FeFET memory device based on ZrO2 anti-ferroelectric and IGZO channel,” in IEDM Tech. Dig., Dec. 2021, pp. 382-385.
[38] High-performance BEOL-compatible atomic-layer-deposited In2O3 Fe-FETs enabled by channel length scaling down to 7 nm: achieving performance enhancement with large memory window of 2.2.V, long retention > 10 years and high endurance > 108 cycles,” in IEDM Tech. Dig., Dec. 2021, pp. 386-389.
[39] M. Si, A. Charnas, Z. Lin, and P. D. Ye, “Enhancement-mode atomic-layer-deposited In2O3 transistors with maximum drain current of 2.2 A/mm at drain voltage of 0.7 V by low-temperature annealing and stability in hydrogen environment,” IEEE Transactions on Electron Devices, vol. 68, no. 3, pp. 1075-1080, Mar. 2021, doi: 10.1109/TED.2021.3053229.
[40] M. Si, Z. Lin, Z. Chen, and P. D. Ye, “First demonstration of atomic-layer-deposited BEOL-compatible In2O3 3D Fin transistors and integrated circuits: high mobility of 113 cm2/V⸳s, maximum drain current of 2.5 mA/μm and maximum voltage gain of 38 V/V in In2O3 inverter,” in VLSI Symp., June 2021, T2-4.
[41] M. Si, Y. Hu, Z. Lin, X. Sun, A, Charnas, D. Zheng, X. Lyu, H. Wang, K. Cho, and P. D. Ye, “Why In2O3 can make 0.7 nm atomic layer thin transistors,” Nano Letters, vol. 21, no. 1, pp. 500-506, Jan. 2021, doi: 10.1021/acs.nanolett.0c03967.
[42] You Meng,a Guoxia Liu,a Ao Liu,a Huijun Song,a Yang Hou,a Byoungchul Shinb, “ Low-temperature fabrication of high performance indium oxide thin film transistors”, RSC Adv., 2015, 5, 37807, DOI: 10.1039/c5ra04145g
[43] H.-I. Yeom, J. B. Ko, G. Mun and S.-H. Ko Park*, “ High mobility polycrystalline indium oxide thin-film transistors by means of plasma-enhanced atomic layer deposition†” , J. Mater. Chem. C, 2016, 4, 6873, DOI: 10.1039/c6tc00580b
[44] Jaakko Leppäniemi , Olli-Heikki Huttunen , Himadri Majumdar , and Ari Alastalo *, Flexography-Printed In2O3 Semiconductor Layers for HighMobility Thin-Film Transistors on Flexible Plastic S 7168-7175, 2015. DOI: 10.1002/adma.201502569
[45] Jiawei He, Guoli Li,* Yawei Lv, Chunlan Wang, Chuansheng Liu, Jinchai Li, Denis Flandre, Huipeng Chen, Tailiang Guo, and Lei Liao* “Defect Self-Compensation for High-Mobility Bilayer InGaZnO/In2O3 Thin-Film Transistor” Chem. C, 6873-6880, 2016., DOI: 10.1002/aelm.201900125