現今工業界正朝著「微小化」的趨勢向前邁進，而奈米技術正是電子元件及電機系統未來繼續發展的基礎，因此從巨觀的元件演變到奈米電子元件是非常關鍵的過程，尤其是現今的45奈米甚至是22奈米世代更顯重要，原因為元件微小化的優點使性能提升及降低消耗功率，也就是說VDD降低，但當scaling到VT不能再小時勢必也造成VDD無法再小，問題就是發生在傳統MOSFET的次臨界擺幅(subthreshold swing, S.S.)最小的物理極限為60 mV/dec.，故若能發展新型元件且subthreshold swing低於60 mV/dec，便可解決此問題。而穿隧場效電晶體(Tunnel-FET)渴望為此問題找到解答，當p/i/n操作在負偏壓(reverse bias)時，可以利用能帶間穿隧(Band-to-Band Tunneling, BTBT)，將subthreshold swing降到60 mV/dec以下。
本論文研究發展陡峭次臨界斜率穿隧電晶體研究：異質穿隧、方向性選擇、鐵電負電容閘極，成功證明epi-Ge Hetero-Tunnel FET在VGS -VBTBT =VDS = -3V有高達20 A/m的汲極電流，和S.S.min = 42mV/dec.。有epi-Ge製程在Si上的HTFET在IDS、S.S.、DIBT的表現皆優於Si的HTFET。即利用Ge能隙較小的觀念造成有效能帶(effective bandgap)降低，進而提高穿隧機率。也成功利用鐵電材料的負電容特性來改善epi-Ge HTFET的性能，如S.S.min、Gm和電流皆有達到效果。現今的epi-Ge/Si HTFET能夠整合目前CMOS製程，因此，為下一世代電晶體發展的選擇之一。

The happy scaling of classic FET has been finished, as strain engineering technology for 90 nm, and gate stack ( high-K + metal gate ) for 45 nm technology node. Intel claimed that the 3D structure of tri-gate is mainstream in 22nm technology node, this is an important revolution for planar transistor in past 40 years. The possible candidates of the trend to achieve the future technology are FinFET, Ge/III-V, nanowire, graphene…etc. In order to More Moore’s Law, we have to the capability of New concept => operation mechanism, New material => channel material, and New structure => 3D for next generation devices. Tunnel-FETs (tFETs) operates with band-to-band tunneling current that change with the channel potential more abruptly than thermionic emission current.
In this paper, we will research the Steep Subthreshold Slope Tunnel Field-Effect Transistor：Hetero-Tunneling, Orientation Effect and Ferroelectric Negative Capacitance Gate Stack. we have successfully demonstrated the first epi-Ge/Si hetero-tunnel FET with high current and < 60 mV/dec swing on (100), (110), and (111) orientations. The drain current of epi-Ge (100) HTFET is as high as 20 A/m(VGS-VBTBT = VDS = -3V), as well as excellent subthreshold swing (S.S.min = 42 mV/dec) and DIBT (28 mV/V). The epi-Ge HTFET is superior to the Si in terms of IDS, subthreshold swing and DIBT. Because, it is beneficial tunneling probability with BTBT current increasing by using band engineering design with heterojunction to narrow effective bandgap. The epi-Ge/Si HTFETs are compatible with current CMOS processes and are therefore a candidate for next-generation applications.

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