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研究生: 吳子帆
Wu,Tzu-Fan
論文名稱: 二階前饋式誤差回授架構之雜訊移頻逐次逼近暫存式類比數位轉換器
A Second-Order CIFF Noise-Shaping SAR ADC Using Error-Feedback Structure
指導教授: 郭建宏
Kuo, Chien-Hung
口試委員: 郭建宏
Kuo, Chien-Hung
黃育賢
Hwang, Yuh-Shyan
陳建中
Chen, Jiann-Jong
口試日期: 2025/01/03
學位類別: 碩士
Master
系所名稱: 電機工程學系
Department of Electrical Engineering
論文出版年: 2025
畢業學年度: 113
語文別: 中文
論文頁數: 110
中文關鍵詞: 類比數位轉換器雜訊移頻逐次逼近暫存器誤差回授積分器前饋
英文關鍵詞: Analog-to-Digital Converters, Noise-Shaping Successive Approximation Register, Error-Feedback, Cascaded Integrators with Distributed Feedforward
研究方法: 實驗設計法
DOI URL: http://doi.org/10.6345/NTNU202500192
論文種類: 學術論文
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  • 隨著物聯網(Internet of Things , IoT) 技術的快速發展,越來越多的應用對高解析度和低功率消耗的類比數位轉換器提出了更高的需求,都需要在節能的情況下提供穩定且精確的數據轉換。因此先進的類比數位轉換器技術在支持這些應用中扮演著關鍵角色,特別是具備超過250kHz頻寬的類比數位轉換器,可以適應多數物聯網設備的數據傳輸需求,實現高效的數據處理。使用雜訊移頻逐次逼近暫存器 (NS-SAR) 相對傳統快閃式(Flash)暫存器可大幅減少功率消耗,以實現低功率消耗高解析度類比數位轉換器為本論文目標。
    提出了一個使用二階積分器前饋 (Cascaded Integrators with Distributed Feedforward, CIFF)雜訊移頻逐次逼近暫存器 (NS-SAR) 類比數位轉換器,結合了誤差回授(Error-Feedback)結構技術。設計中使用了一階主動電路,透過操作轉導放大器搭配一階被動電路,由單位增益緩衝器輔助,以開關切換模式實現了鋒利的雜訊轉移函數。透過電容之間的電荷累積,並將九位元量化器產生的量化誤差進行回授,結合主動電路的高解析度與穩定性以及被動電路的低功率消耗特性。晶片採用台積電0.18um標準CMOS製成,在10 MHz取樣頻率下,於250kHz的頻寬內實現了78.13 dB的訊號雜訊失真比,功率消耗為232uW,工作電壓為1.5V。在250kHz和625kHz頻寬下,FoMs皆超過165 dB。在625kHz頻寬下的FoMw為48.5 [fJ/step]。

    With the rapid development of Internet of Things (IoT) technology, an increasing number of applications demand high-resolution and low-power ADCs that can provide stable and accurate data conversion under energy-saving conditions. Particularly, ADCs with bandwidths exceeding 250kHz can meet the data transmission requirements of most IoT devices, enabling efficient data processing. Using NS-SAR technology can significantly reduce power consumption compared to traditional Flash ADCs. This paper aims to achieve a low-power, high-resolution ADC.
    A second-order CIFF NS-SAR ADC with an EF structure technique is proposed. The design incorporates a first-order active circuit using an Operational Transconductance Amplifier alongside a first-order passive circuit, assisted by a Unity-Gain Buffer in a switched-mode configuration. By accumulating charge between capacitors and feeding back the quantization error generated by a 9-bit quantizer, the design combines the high resolution and stability of the active circuit with the low power consumption of the passive circuit. The chip is fabricated using TSMC 0.18μm standard CMOS technology. At a 10 MHz sampling frequency, it achieves an SNDR of 78.13 dB over a 250kHz bandwidth with a power consumption of 232μW at a supply voltage of 1.5V. The FoMs exceed 165 dB at both 250kHz and 625kHz bandwidths, and the FoMw reaches 48.5 fJ/step at 625kHz.

    第一章  緒論 1 1.1  研究動機與背景 1 1.2  論文架構與研究方法 2 第二章  基本類比數位轉換器概論 4 2.1 前言 4 2.2 效能指標 6 2.2.1 訊號雜訊比 6 2.2.2 訊號雜訊失真比 7 2.2.3 無雜波干擾之動態範圍 7 2.2.4 有效位元 8 2.2.5 動態範圍 9 2.2.6 品質因數 10 2.3  量化器 10 2.3.1 單位元量化器 11 2.3.2 多位元量化器 12 2.3.3 量化誤差 14 2.4 雜訊移頻 16 2.4.1 一階雜訊移頻 19 2.4.2 二階雜訊移頻 21 2.5 誤差回授 23 2.6 逐次逼近類比數位轉換器 25 2.6.1 逐次逼近式演算法 26 2.6.2 SAR ADC工作流程 27 2.7 章節總結 28 第三章 電路元件設計 29 3.1 前言 29 3.2 交換式電容電路 29 3.2.1 反向積分器 29 3.2.2 非反向積分器 32 3.3 開關 34 3.3.1 MOS開關 34 3.3.2 傳輸閘開關 36 3.3.3 靴帶式開關 39 3.4 誤差回授電路 41 3.4.1 單位增益緩衝器 42 3.5 比較器 43 3.5.1 動態比較器 44 3.6 真單相時脈電路 47 3.7 逐次逼近式暫存器 48 3.8 數位類比轉換器 50 3.8.1 數位類比轉換器邏輯電路 50 3.8.2 電容式數位類比轉換器 51 3.9 章節總結 53 第四章  二階CIFF-EF逐次逼近暫存類比數位轉換器設計與實現 54 4.1 前言 54 4.2 線性Matlab模擬 56 4.3 電路非理想效應 58 4.3.1 熱雜訊 59 4.3.2 運算放大器有限增益 61 4.3.3 時脈抖動 62 4.4 電路架構 64 4.4.1 電路電位運用技術 65 4.4.2 轉導運算放大器 67 4.4.3 單位增益放大器 69 4.4.4 誤差回授切換方法 72 4.4.5 電路時序分析 74 4.4.6 電路架構模擬結果 76 4.5 電路佈局與實現 77 4.5.1 佈局設計與影響 77 4.5.2 外部設計考量 82 4.5.3 電路佈局模擬結果 86 4.6 晶片量測環境與結果 87 4.6.1 濾波槽電路與穩壓電路 88 4.6.2 輸入終端電路 90 4.6.3 PCB設計 91 4.6.4 量測結果 95 第五章  總結與未來展望 100 5.1  總結 100 5.2  未來展望 102 參考資料 105 自傳 108 學術成就 109

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