金氧半場效電晶體（MOSFET）節點技術不斷縮小至22奈米以下，因此在半導體應變工程中，接觸蝕刻終止層（CESL）與淺溝槽隔離（STI）被視為重要技術，兩種應力源可提高有效地電晶體的載子遷移率。而利用有限元素模擬的方法下，本研究探討在n型MOSFET中，STI幾何結構對於電晶體性能的影響。在上述條件下主要是利用不同製程方法讓矽通道的產生通道應力轉換以及CESL的內應力的影響進行分析。由模擬結果得知，具有深度的STI結構較無深度的STI更有用處，因為應力源所造成的Si通道的應力分佈是較高的。此外，藉由壓阻效應，可提高電晶體的載子遷移率的性能提高，由於上述的壓阻效應，可做出結論整合STI和CESL應力源可以有效的提高中10％〜20％載子遷移率。最後，對於電晶體應力分佈影響最重要的四個因子，閘極寬度、源∕汲極的長度、STI的長度、STI的深度。經過變異數分析結果後，源∕汲極長度與STI的深度這兩個因子對於載子遷移率增益的影響程度最為顯著。

The adoption of shallow trench isolation (STI) integrated with a contact etching stop layer (CESL) is regarded as an important technique in strain engineering that significantly boosts transistor mobility of nanoscale devices because the node technology of the metal-oxide-semiconductor field-effect transistor (MOSFET) is continually scaled down to 22 nm and beyond. A finite element method based on stress simulation is implemented in this research to investigate the effects of STI geometric profiles on n-type MOSFET performance. The mechanism for transferring STI and CESL intrinsic stresses under the aforementioned conditions to the silicon (Si) channel is explained by considering the major procedures of process-induced stress. Results indicate that the approaches of suitable sunken STI patterns are more useful than those of a flat STI prototype because a difference in the resultant stress distribution for the Si channel region is introduced by the device profiles. The piezoresistance effect of Si is being actively explored at present to improve the characteristic of transistors because this effect has been extensively used in mechanical stress technology. A crystal strain resulting in a change in electrical conductivity is observed because of the aforementioned piezoresistance effect. Induced mobility gains from STI and CESL stressors are systematically observed. Integrating a tensile CESL and an STI stressor region results in almost 10% to 20% enhancement in carrier mobility. The critical geometric factors of the NMOSFET structure significantly affect the stress distribution in the channel region. Therefore, four critical designed factors including S/D lengths, gate width, STI length and depth of STI are analyzed to ANOVA. However, the effect of the S/D length on the device performance enhancement of NMOSFETs with a sunken STI stressor combined with a tensile CESL can be accurately calculated using 3D stress simulations.

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