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研究生：	林孟霆 Lin, Meng-Ting
論文名稱：	24-GHz低雜訊放大器之靜電放電防護設計 On-Chip ESD Protection Design for 24-GHz LNA
指導教授：	林群祐 Lin, Chun-Yu
學位類別：	碩士 Master
系所名稱：	電機工程學系 Department of Electrical Engineering
論文出版年：	2017
畢業學年度：	105
語文別：	英文
論文頁數：	85
中文關鍵詞：	靜電放電、矽控整流器、低雜訊放大器
英文關鍵詞：	Electrostatic discharge, silicon-controlled rectifier, low-noise amplifier
DOI URL：	https://doi.org/10.6345/NTNU202203079
論文種類：	學術論文
相關次數：	點閱：70 下載：13
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本論文主旨為應用於射頻積體電路之全晶片靜電防護電路，本論文設計了兩種應用於高頻積體電路的靜電放電防護設計，並與先前論文所提出的傳統防護電路來做比較。所下線之晶片皆使用0.18um CMOS製程。

傳統靜電放電箝制電路已被廣泛應用於靜電放電防護設計之中，然而其高佈局面積在先進製程中往往會是個麻煩，因此本篇論文利用矽控整流器低佈局面積與優秀靜電防護能力特性，來加以改善傳統電路，而矽控整流器的閂鎖效應與導通速度過慢問題，本論文也提出了解決方法；本論文提出使用內嵌入式矽控整流器二極體串來改良原先P型與N型二極體的靜電放電能力，透過量測結果比較，本論文提出的兩種靜電放電防護設計皆能在單一面積下提供最佳的靜電耐受度並擁有且較低損耗值。

為了驗證靜電防護電路應用於高頻電路的實際功用，本論文也設計了24GHz低雜訊放大器並搭配適當尺寸的防護電路，在量測結果中，本論文所提出的防護設計並不會影響高頻電路之響應。

This essay is to design an effective whole-chip ESD protection circuits for RF integrated circuit. In this essay, two types of ESD protection designs, which apply to RF integrated circuits has been proposed and compared with conventional ESD protections. All of circuits in this essay are fabricated in 0.18-um CMOS process.

The conventional power-rail ESD clamp circuit has been used widely in ESD protection designs. However, the high layout area of conventional circuit is an issue in advanced process. Therefore, using silicon-controlled rectifier (SCR) with low layout area and excellent ESD protection ability improves the issue of the conventional power-rail ESD clamp circuit that is high layout area. Furthermore, solutions of the latch-up problem and slow-trigger-on speed of SCR have been proposed. In this essay, using the diode string with embedded SCR improves the issue of p-type and n-type diodes. Through the comparison of measurement results, two types of ESD protection designs can provide the best ESD robustness and the lowest loss at unit area.

In order to verify the practical function of ESD protection circuit on RF circuit, the low-noise amplifier (LNA) with the appropriate size of ESD protection circuit has been designed. In measurement results, proposed designs do not affect the RF performance.

Contents
Abstract (Chinese)  I
Abstract (English)  II
Acknowledgement  III
Contents  V
Table Captions  VIII
Figure Captions  IX
Chapter 1 Introduction  1
1 Motivation  1
2 Background of ESD  2
3 Testing Methods  2
4 Background of Whole-Chip ESD Protection Circuit  4
5 Organization of This Dissertation  9
Chapter 2 Whole-Chip ESD Protection Circuit Design  10
1 ESD Protection Component  10
1.1 Diode  10
1.2 SCR  12
1.3 DSSCR  14
2 Design of Power-Rail ESD Clamp  16
3 Whole-Chip ESD Protection Circuit  18
3.1 Prior Arts  18
Dual Diodes with MOS-Based Power-Rail ESD Clamp (DD_MOS)  18
Dual Stacked Diodes with MOS-Based Power-Rail ESD Clamp (DSD_MOS)  19
3.2 Proposed Designs  22
Dual Stacked Diodes with SCR-Based Power-Rail ESD Clamp (DSD_SCR)  22
DSSCR with SCR-Based Power-Rail ESD Clamp (DSSCR_SCR)  22
4 Experimental Results  25
4.1 High-Frequency Performances  25
4.2 TLP I-V Curves  28
4.3 HBM Measurement Results  30
4.4 CDM Measurement Results  31
4.5 Leakage  32
4.6 Comparison  33
5 Summary  36
Chapter 3 24-GHz Low-Noise Amplifier  37
1 Introduction  37
2 Transistor Noise Sources  38
2.1 Thermal Noise  38
2.2 MOSFET Gate Resistance Noise  40
2.3 Flicker Noise  40
3 Parameters of Designing Low-Noise Amplifier  41
3.1 Gain  41
Transducer Power Gain  41
Available Power Gain  41
Operating Power Gain  42
3.2 Stability  42
3.3 Noise Figure  43
4 Circuit Design Steps  44
4.1 Design of Transistor Bias  44
4.2 Design of Transistor Size  46
4.3 Design of Source Degeneration Inductor  47
4.4 Design of Matching Network  48
Input-Stage Matching Network  49
Stage-to-Stage Matching Network  50
Output-Stage Matching Network  51
4.5 Design of Bias Circuit  52
5 LNA Simulation Results  53
5.1 LNA  53
5.2 LNA with ESD Protection Circuit  55
6 LNA Measurement Results  60
6.1 LNA  60
6.2 LNA with ESD Protection Circuit  63
TLP I-V Curves  64
High-Frequency Performance  66
7 Discussion and Summary  74
7.1 Debug  74
7.2 Summary  75
Chapter 4 Conclusion and Future Works  77
1 Conclusion  77
2 Future Works  78
Reference  80
Vita  84
Publication List  85
                                

[1] S. Voldman, ESD Phtsics and Devices, John Wiley & Sons, 2005.
[2] M.-D. Ker, W.-Y. Lo, C.-M. Lee, C.-P. Chen, and H.-S. Kao, “ESD protection design for 900-MHz RF receiver with 8-kV HBM ESD robustness,” in Proc. IEEE Radio Frequency Integrated Circuit Symp., 2002, pp. 427-430.
[3] L. Li, H. Liu, Z. Yang, L. Chen, “A novel co-design and evaluation methodology for ESD protection in RFIC,” Microelectronics Reliability, vol. 52, pp. 2632–2639, July 2012.
[4] M.-D Ker, C.-Y. Lin, and Y.-W. Hsiao, “Overview on ESD protection designs of low parasitic capacitance for RFICs in CMOS technologies,” IEEE Trans. Device and Materials Reliability, vol. 11, no. 2, pp. 207-218, Jun. 2011.
[5] M.-D. Ker and C.-M. Lee, “ESD protection design for Giga-Hz RF CMOS LNA with novel impedance-isolation technique,” in Proc. EOS/ESD Symp., 2003, pp. 204–213.
[6] Industry Council on ESD Target Levels, “White Paper 1: A case for lowering component level HBM/MM ESD specifications and requirements,” Sep. 2011.
[7] Industry Council on ESD Target Levels, “White Paper 2: A case for lowering component level CDM ESD specifications and requirements,” Apr. 2010.
[8] C.-Y. Lin, T.-L. Chang, and M.-D. Ker, “Investigation on CDM ESD events at core circuits in a 65-nm CMOS process,” Microelectronics Reliability, pp. 2627–2631, 2012.
[9] C.-Y. Lin, L.-W. Chu, S.-Y. Tsai and M.-D. Ker, “Design of Compact ESD Protection Circuit for V-Band RF Applications in a 65-nm CMOS Technology,” IEEE Tran. Dev. Mat. Rel., Vol 12, No. 3, pp. 554-561, 2012.
[10] C. Lin, L. Chu, and M. Ker, “ESD protection design for 60-GHz LNA with inductor-triggered SCR in 65-nm CMOS process,” IEEE Trans. Microw. Theory Tech., vol. 60, no. 3, pp. 714–723, Mar. 2012.
[11] W.-Y. Chen, M.-D. Ker, Y.-J. Huang, Y.-N. Jou and G.-L. Lin, “Measurement on Snapback Holding Voltage of High-Voltage LDMOS for Latch-up Consideration,” In Proc., IEEE Proceedings of Asia Pacific Conference on Circuits and Systems, 2008, pp. 61-64.
[12] J. Lee, Y. Huh, P. Bendix, and S. Kang. “Design-For-ESD Reliability for High-Frequency I/O Interface Circuits in Deep Submicron CMOS Technology,” In Proc. Int. Symp. Circuits and Systems, 2000, pp.746-749.
[13] W. Soldner, M. Streibl, U. Hodel, M. Tiebout, H. Gossner, D. SchmittLandsiedel, J. H. Chun, C. Ito, and R. W. Dutton, “RF ESD protection strategies: Codesign vs. low-C protection,” in Proc. EOS/ESD Symp.,2005, pp.1-10.
[14] M.-D. Ker and K.-C. Hsu, “Overview of On-Chip Electrostatic Discharge Protection Design with SCR-Based Devices in CMOS Integrated Circuits,” IEEE Transactions on Device and Materials Reliability, vol. 5, no. 2, pp. 235-249, Jun. 2005.
[15] M. Tsai, S. Hsu, F. Hsueh, and C. Jou, “A multi-ESD-path low-noise amplifier with a 4.3-A TLP current level in 65-nm CMOS,” IEEE Trans. Microwave Theory and Techniques, vol. 58, no. 12, pp. 4004-4011, Dec. 2010.
[16] M.-D. Ker and K. Hsu, “Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-quarter-micron CMOS process,” IEEE Trans. on Electron Devices, vol. 50, no.2, pp. 397-405, Feb. 2003.
[17] C.-Y. Lin, M.-L. Fan, M.-D. Ker, L.-W. Chu, J.-C. Tseng, and M.-H. Song, “Improving ESD robustness of stacked diodes with embedded SCR for RF applications in 65-nm CMOS,” in Proc. IRPS, 2014, pp. 1-5.
[18] M.-D. Ker, “Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI,” IEEE Trans. Electron Devices, vol. 46, no. 1, pp. 173–183, Jan. 1999.

[19] F. Altolaguirre and M.-D. Ker, “Power-rail ESD clamp circuit with embedded-trigger SCR device in a 65-nm CMOS process,” in Proc. Midwest Symp. Circuits and Systems (MWSCAS), 2014, pp. 250-253.
[20] M. P. J. Mergens, C. C. Russ, K. G. Verhage, J. Armer, P. C. Jozwiak, R. Mohn, B. Keppens, and C. S. Trinh, “Diode-triggered SCR for RF-ESD protection of BiCMOS SiGe HBTs and CMOS ultrathin gate oxides,” in Proc. IEDM Tech. Dig, 2003, pp. 515–518.
[21] M.-D. Ker and C.-H. Chuang, “Stacked-NMOS triggered silicon-controlled rectifier for ESD protection in high/low-voltage-tolerant I/O interface,” IEEE Electron Device Letter, vol. 23, no. 6, pp. 363–365, Jun. 2002
[22] F. Altolaguirre and M.-D. Ker, “Low-leakage power-rail ESD clamp circuit with gated current mirror in a 65-nm CMOS technology,” in Proc. IEEE ISCAS, 2013, pp. 2638–2641.
[23] P.-Y. Chiu and M.-D. Ker, “Design of low-leakage power-rail ESD clamp circuit with MOM capacitor and STSCR in a 65-nm CMOS process,” in Proc. IEEE Int. Conf. Integrated Circuit Design and Technology, 2011.
[24] L. Tiemeijer and R. Havens, “A calibrated lumped-element de-embedding technique for on-wafer RF characterization of high-quality inductors and high-speed transistors,” IEEE Trans. Electron Devices, vol. 50, no. 3, pp. 822-829, Mar. 2003.
[25] D. Ahn, K. Choi, K. Choi, and S.-M, Han, “A new de-embedding technique for arbitrary N-port networks using ideal 1:J transformers” in Proc. IEEE Int. Conf. Electrical Design of Advanced Packaging and Systems (EDAPS), 2016.
[26] Z. Yang and E.-L, Tan, “A De-embedding technique for diode-incorporated reconfigurable antenna simulation” in Proc. IEEE Int. International Symposium on Antennas and Propagation (APSURSI), 2016, pp.1437-1438.
[27] B. Razavi, Design of Analog CMOS Integrated Circuits, McGrw-Hill, 2001.
[28] S. A. Mass, Noise in Linear and Nonlinear Circuits, Artech House, 2005.
[29] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, 2nd ed, Cambridge University Press, 2004.
[30] C. Lin, M. Lin, C. Liang, and S. Chung, “A 24 GHz Low-power and High-gain Low-noise Amplifier Using 0.18 µm CMOS Technology for FMCW Radar Applications,” in Proc. IEEE Int. Conf. RF and Microwave, 2012.
[31] S. Shin, M. Tsai, R. Liu, K. Lin, and H. Wang, “A 24-GHz 3.9-dB NF low-noise amplifier using 0.18 μm CMOS technology,” IEEE Microwave and Wireless Components Letters, vol. 15, no. 7, pp. 448-450, July 2005.
[32] K.-W. Yu, Y.-L. Lu, D.-C. Chang, V. Liang, and M. F. Chang, “K-band low-noise amplifiers using 0.18 μm CMOS technology,” IEEE Microwave and Wireless Components Letters, vol. 14, no. 3, pp. 106–108, Mar. 2004.
[33] A. Sayag S. Levin, D. Regev, D. Zfira, S. Shapira, D. Goren, and D. Ritter, “A 25 GHz 3.3 dB NF low noise amplifier based upon slow wave transimission lines and the 0.18 μm CMOS technology” in Proc. IEEE RFIC Symp, 2008, pp. 373-376.
[34] W.-H. Cho, Hsu, and S.S.H., “An Ultra-Low-Power 24 GHz Low-Noise Amplifier Using 0.13μm CMOS technology,” IEEE Microwave and Wireless Components Letters, vol. 20, no. 12, pp. 681-683, Dec. 2010.
[35] H. Wang, L. Zhang, L. Zhang, Y. Wang, and Z. Yu, “Design of 24-GHz High-Gain Receiver Front-End Utilizing ESD-Split Input Matching Network,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 58, no. 8, pp. 482–486, Aug. 2011.
[36] V. Issakov, M. Tiebout, Y. Cao, A. Thiede, and W. Simburger, “A low power 24 GHz LNA in 0.13 μm CMOS,” in Proc. IEEE Microwaves, Communications, Antennas and Electronic Systems Conf., 2008, pp. 1-10.
[37] V. Issakov, H. Knapp, M. Wojnowski, A. Thiede, W. Simbiirger, G. Haider, and L. Maurer, “ESD-protected 24 GHz LNA for radar applications in SiGe:C technology,” in Proc. IEEE SiRF Conf., 2009, pp. 1–4.

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