隨著科技持續的進步，新開發的裝置皆著重於更低的功耗以及更小的面積以達到尺寸微縮的目的。近年來大數據盛行使得越來越多的邊緣裝置(edge devices)被廣為使用，開發這類裝置都需具備低功耗的特性以達到節能的目的。因此，為了符合這樣的要求，選擇鐵電材料便成了一項不錯的選擇，由於其偶極矩會隨著電壓而轉變方向的特點，在未施加電壓時仍能保存原本儲存狀態直到有反向電壓施加才會導致偶極矩再度旋轉。本研究以鐵電材料與電晶體結合成鐵電電晶體(Ferroelectric Field Effect Transistor, FeFET)，研究適當的結構以將其應用於非揮發記憶體中。
本實驗選擇HZO材料製作成MFM (Metal-Ferroelectric-Metal)電容並與金屬氧化物半導體場效電晶體連接成1T1CFE的記憶體架構，透過基本的電性量測確認其具備記憶體操作的能力，足夠的記憶視窗(memory window)作為判斷此一特性的首要特性。我們初步實驗顯示在不同電壓的施加之下會使得元件呈現不同的電流特性，但進一步的研究發現1T1CFE的架構存在漏電的問題，導致其開關比較小，相較於其他種記憶體強調更高的開關比，改善缺點便是本實驗之研究目的。
為了改善1T1CFE漏電較高的狀況，吾人將原本1T1CFE的架構多增加一顆控制電晶體來改善此一狀況，將控制電晶體與原本1T1CFE相連接形成2T1CFE的架構，在I-V電性量測下仍保有原本記憶視窗的大小，且由於更低的漏電使得開關比更大達到105倍，而要能操作記憶體需要先透過電壓操作編程(program)及抹除(erase)兩種模式，調變脈衝寬度可以得到最低20ns即可成功program，7ns即可成功erase，此時逐步調變脈衝電壓使得電流產生變化，這也使得2T1CFE的FeRAM具有多狀態操作(multi-level operation)，在此一操作狀態下也符合現今晶片微縮的趨勢。
實驗結果顯示，我們成功在2T1CFE的架構下，可將其操作在多狀態(Multi-level)，這八種狀態的電流均勻的分布於10-10A 到10-5A之間，在耐久度測試下可以操作107次且在烘烤85℃的狀態下也可以讓分布的八個電流狀態維持超過106秒。另外，為了要能順利應用在記憶體陣列中，電性干擾(Disturbance)的測試是為了確保未選定的記憶體元件受到編成或讀取的干擾。在2T1CFE的架構下，皆可以不受干擾的維持104秒以上，而在功耗測試中，2T1CFE在操作的消耗功率皆低於1T1CFE，可以看出其在未來具有良好的應用潛力並滿足IoT低功耗的需求。

As the technology keeps improving, newly invented devices attract increasing research effort aimed at low power and smaller chip area at lower cost. On the other hand, in recent years, more and more edge devices are needed to be involved in the internet of things era, abbreviated as IOT. Developing new devices that are energy efficient to achieve this trend is a prerequisite. In this work, we choose ferroelectric as our material and together with FET to configure them as FeFET and use it to realize nonvolatile memory operation. Ferroelectric has its advantage of domain switching that does not require external power to hold its state, so while applying voltage on ferroelectric material it stays permanent as long as a reverse bias voltage is applied. The purpose of this work is to develop suitable ferroelectric and transistor architecture for nonvolatile memory operation.
To achieve memory operation, we use HZO as a ferroelectric layer, forming as a capacitor, and use it to configure with FinFET as an 1T1CFE structure. Through basic electrical measurement, this 1T1CFE structure was proven to provide sufficiently large memory window. However, we also found an existing huge leakage current which led to a reduction of the on/off ratio. The motivation to improve this leakage current becomes the first priority in this study.
In order to enhance on/off ratio, we developed a new structure that can effectively reduce the leakage current. A control transistor is used in addition to the original 1T1CFE structure which is formed as a 2T1CFE structure of FeRAM. By measuring its I-V curve, lower leakage and larger in/off around 105x can be observed. To perform it as a memory, program and erase operation can achieve a speed of up to 20ns for programming and 7ns for erase. With a small increase of the operating pulse voltage, the proposed 2T1CFE FeRAM is capable of multi-level operation. In addition, multi-level cell operation benefits the increasing storage density of nonvolatile memory.
After successfully achieved multi-level state operation, 2T1CFE FeRAM can be modulated into eight states. In our tests, uniformly distributed eight states ranging from 10-10A to 10-5A and up to 107 cycles of endurance can be achieved. Also, under 85℃of baking, 106 seconds of data retention can be achieved. In order to operate 2T1CFE memory cell in a memory array, worst case of disturbance test is needed to prevent unselected cell being disturbed. Program, erase and read operations all passed disturbance test and can hold up to 104 seconds. In terms of the power consumption, the multilevel 2T1CFE FeRAM is superior to the 1T1CFE architecture which meets the low power requirement of IoT for future nonvolatile memory applications.

[1.1] E. R. Hsieh, M. Giordano, B. Hodson, A. Levy, S. K. Osekowsky, R. M. Radway, Y.C. Shih, W. Wan, T. F. Wu, X. Zheng, M. Nelson, B. Q. Le, H. -S. P. Wong, S. Mitra, and S. Wong, “High-Density Multiple Bits-per-Cell 1T4R RRAM Array with Gradual SET/RESET and its Effectiveness for Deep Learning,” in IEDM Tech. Digest, pp. 843-846, 2019.
[1.2] N. Xu, Y. Lu, W. Qi, Z. Jiang, X. Peng, F. Chen, J. Wang, W. Cho, S. Yu, and D. S. Kim, “STT-MRAM Design Technology Co-optimization for Hardware Neural Networks,” in IEDM Tech. Digest, pp. 348-351, 2019.
[1.3] V. P. H. Hu, H. H. Lin, Z. A. Zheng, Z. T. Lin, Y. C. Lu, L. Y. Ho, Y. W. Lee, C. W. Su, and C. J. Su, “Split-Gate FeFET ( SG-FeFET ) with Dynamic Memory Window Modulation for Non-Volatile Memory and Neuromorphic Applications,” in Symposium on VLSI Technology, pp. T134–T135, 2019.
[1.4] H. Mulaosmanovic, S. Slesazeck, J. Ocker, M. Pesic, S. Muller, S. Flachowsky, J. Müller, P. Polakowski, J. Paul, S. Jansen, S. Kolodinski, C. Richter, S. Piontek, T. Schenk, A. Kersch, C. Kunneth, R. van Bentum, U. Schroder, and T. Mikolajick, “Evidence of Single Domain Switching in Hafnium Oxide Based FeFETs: Enabler for Multi-Level FeFET Memory Cells,” in IEDM Tech. Digest, pp. 688-690, 2015.
[1.5] S. Mueller, J. Müller, U. Schroeder, and T. Mikolajick, “Reliability Characteristics of Ferroelectric Si:HfO2 Thin Films for Memory Applications,” IEEE Trans. Device Mater. Reliab., vol. 13, no. 1, pp. 93-97, 2013.
[1.6] S. C. Chang, N. Haratipour, S. Shivaraman, T. L. Brown-Heft, J. Peck, C. C. Lin, I. C. Tung, D. R. Merrill, H. Liu, C. Y. Lin, F. Hamzaoglu, M. V. Metz, I. A. Young, J. Kavalieros, and U. E. Avci, “Anti-ferroelectric HfxZr1-xO2 Capacitors for High-density 3-D Embedded-DRAM,” IEEE International Electron Devices Meeting, pp. 605-608, 2020.
[2.1] J. Müller, E. Yurchuk, T. Schlösser, J. Paul, R. Hoffmann, S. Müller, D. Martin, S. Slesazeck, P. Polakowski, J. Sundqvist, M. Czernohorsky, K. Seidel, P. Kücher, R. Boschke, M. Trentzsch, K. Gebauer, U. Schröder, and T. Mikolajick, “Ferroelectricity in HfO2 Enables Nonvolatile Data Storage in 28 nm HKMG,” in Symposium on VLSI Technology, pp. 25-26, 2012.
[2.2] J. Müller, T. S. Böscke, D. Bräuhaus, U. Schröder, U. Böttger, J. Sundqvist, P. Kücher, T. Mikolajick, and L. Frey, “Ferroelectric Zr0.5Hf0.5O2 Thin Films for Nonvolatile Memory Applications,” Appl. Phys. Lett., vol. 99, no. 11, 112901, 2011.
[2.3] J. Müller, U. Schröder, T. S. Böscke, I. Müller, U. Böttger, L. Wilde, J. Sundqvist, M. Lemberger, P. Kücher, T. Mikolajick, and L. Frey, “Ferroelectricity in Yttrium-Doped Hafnium Oxide,” J. Appl. Phys., vol. 110, no. 11, 114113, 2011.
[2.4] S. Mueller, C. Adelmann, A. Singh, S. VanElshocht, U. Schroeder, and T. Mikolajick, “ Ferroelectricity in Gd-Doped HfO2 Thin Films ,” ECS J. Solid State Sci. Technol., vol. 1, no. 6, pp. N123-N126, 2012.
[2.5] T. S. Böscke, St. Teichert, D. Bräuhaus, J. Müller, U. Schröder, U. Böttger, and T. Mikolajick, “Phase Transitions in Ferroelectric Silicon Doped Hafnium Oxide,” Appl. Phys. Lett., vol. 99, no. 11, 112904, 2011.
[2.6] J. Müller, T. S. Böscke, U. Schröder, S. Mueller, D. Bräuhaus, U. Böttger, L. Frey, and T. Mikolajick, “Ferroelectricity in Simple Binary ZrO2 and HfO2,” Nano Lett., vol. 12, no. 8, pp. 4318-4323, 2012.
[2.7] T. S. Böescke, J. Müller, D. Bräuhaus, U. Schröder, and U. Böttger, “Ferroelectricity in Hafnium Oxide: CMOS Compatible Ferroelectric Field Effect Transistors,” in IEDM Tech. Digest, pp. 547-550, 2011.
[2.8] X. Lyu, M. Si1, X. Sun, M. A. Capano, H. Wang, and P. D. Ye, “Ferroelectric and Anti-Ferroelectric Hafnium Zirconium Oxide: Scaling Limit, Switching Speed and Record High Polarization Density,” in Symposium on VLSI Technology, pp. T44-T45, 2019.
[2.9] C. Liu, F. Liu, Q. Luo, P. Huang, X. X. Xu, H. B. Lv, Y. D. Zhao, X. Y. Liu and J. F. Kang, “Role of Oxygen Vacancies in Electric Field Cycling Behaviors of Ferroelectric Hafnium Oxide,” in IEDM Tech. Digest, pp. 376-379, 2019.
[3.1] T. Alia, P. Polakowski, S. Riedel, T. Büttner, T. Kämpfe, M. Rudolph, B. Pätzold, K. Seidel, D. Löhr, R. Hoffmann, M. Czernohorsky, K. Kühnel, X. Thrun, N. Hanisch, P. Steinke, J. Calvo and J. Müller, “Silicon Doped Hafnium Oxide (HSO) and Hafnium Zirconium Oxide (HZO) Based FeFET: A Material Relation to Device Physics,” Appl. Phys. Lett., vol. 112, no. 22, 222903, 2018.
[3.2] K. Chatterjee, S. Kim, G. Karbasian, A. J. Tan, A. K. Yadav, A. I. Khan, C. Hu and S. Salahuddin, “Self-Aligned, Gate Last, FDSOI, Ferroelectric Gate Memory Device with 5.5-nm Hf0.8Zr0.2O2, High Endurance and Breakdown Recovery,” IEEE Electron Devices Lett., vol. 38, no. 10, pp. 1379-1382, 2017.
[4.1] S. Mueller, S. Slesazeck, T. Mikolajick, J. Müller, P. Polakowski, and S. Flachowsky, “Next-generation ferroelectric memories based on FE-HfO2,” IEEE International Symposium on Applications of Ferroelectrics, pp. 233-236, 2015.
[4.2] S. J. Yoon, D. H. Min, S. E. Moon, K. S. Park, J. I. Won, and S. M. Yoon, “Improvement in Long-Term and High-Temperature Retention Stability of Ferroelectric Field-Effect Memory Transistors With Metal-Ferroelectric–Metal–Insulator–Semiconductor Gate-Stacks Using Al-Doped HfO2 Thin Films,” IEEE Transactions on Electron Devices, vol. 67, pp. 499-504, 2020.
[4.3] M. Saitoh, R. Ichihara, M. Yamaguchi, K. Suzuki, K. Takano, K. Akari, K. Takahashi, Y. Kamiya, K. Matsuo, Y. Kamimuta, K. Sakuma, K. Ota, and S. Fujii , "HfO2-based FeFET and FTJ for Ferroelectric-Memory Centric 3D LSI towards Low-Power and High-Density Storage and AI Applications," in IEDM Tech. Digest, pp. 18.1.1-18.1.4, 2020.
[4.4] T. Ali, P. Polakowski, S. Riedel, T. Büttner, M. Rudolph, B. Pätzold, T. Kämpfe, K. Seidel, D. Löhr, R. Hoffmann, M. Czernohorsky, K. Kühnel, P. Steinke, J. Calvo, K. Zimmermann, K. Biedermann, and J. Müller, “Low Power and High Endurance MFIS SiON Based Ferroelectric HfZrO2 FeFET,” IEEE Silicon Nanoelectronics Workshop, 2018.