[1] S. H. Voldman, ESD Physics and Devices. New York: Wiley, 2005.
[2] A. Amerasekera and C. Duvvury, ESD in Silicon Integrated Circuits, John Wiley & Sons, 2002.
[3] O. Semenov, H. Sarbishaei, and M. Sachdev, ESD Protection Devices and Circuit Design for Advanced CMOS Technologies. Amsterdam: Springer, 2008.
[4] T. Lim, J. Jimenez, P. Benech, J. -M. Fournier, B. Heitz and P. Galy, "Geometrical impact on RF performances of broadband ESD self protected transmission line in advanced CMOS technologies," 2012 IEEE International Integrated Reliability Workshop Final Report, South Lake Tahoe, CA, USA, 2012.
[5] Microelectronics Test Method Standard MIL-STD-883D Method 301 5.7“Electrostatic discharge sensitivity classification,” US Department of Defense, 1991.
[6] ESD Association and JEDEC Solid State Technology Association, “Human body model (HBM) - component level,” ANSI/ESDA/JEDEC JS-001-2017, 2017.
[7] Industry Council on ESD Target Levels, “White Paper 1: A case for lowering component level HBM/MM ESD specifications and requirements,” June. 2018.
[8] E. Grund, T. Chang, R. Watkins, C. Burke, J. Katz and R. Gauthier, "A New CDM Discharge Head for Increased Repeatability and Testing Small Pitch Packages," 2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), Reno, NV, USA, 2018.
[9] ESD Association and JEDEC Solid State Technology Association, “Charged device model (CDM) -component level,” ANSI/ESDA/JEDEC JS-002-2014, 2014.
[10] Industry Council on ESD Target Levels, “White Paper 2: A case for lowering component level CDM ESD specifications and requirements,” May. 2021.
[11] H. Wang, C. Jiao, L. Zhang, D. Zeng, D. Yang, Y. Wang, and Z. Yu, "A low-power ESD-protected 24GHz receiver front-end with π-type input matching network," 2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2011.
[12] M. D. Ker, "Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI," in IEEE Transactions on Electron Devices, vol. 46, no. 1, pp. 173-183, Jan. 1999.
[13] F. Roger, W. Reinprecht and R. Minixhofer, "Process variation aware ESD design window considerations on a 0.18μm analog, mixed-signal high voltage technology," EOS/ESD Symposium Proceedings, 2011, pp. 1-7.
[14] P. Mahajan, S. Suresh, A. Quah, F. Rival, R. Jain, U. Singh, R. Gauthier, and K. J. Hwang, "Robust ESD Implanted 5V GGNMOS Clamp Design and Process optimization with maximized ESD Design Window," 2019 Electron Devices Technology and Manufacturing Conference (EDTM), 2019, pp. 172-175.
[15] C. -T. Wang, Y. -C. Chen, T. -H. Tang and K. -C. Su, "ESD protection design with adjustable snapback behavior for 5-V application in 100nm CMOS process," 2013 IEEE International Reliability Physics Symposium (IRPS), 2013.
[16] A. Z. H. Wang, H. Feng, R. Zhan H. Xie, G. Chen, Q. Wu, X. Guan, Z. Wang, and C. Zhang, "A review on RF ESD protection design," in IEEE Transactions on Electron Devices, vol. 52, no. 7, pp. 1304-1311, July 2005.
[17] C. -Y. Lin, M. -L. Fan, M. -D. Ker, L. -W. Chu, J. -C. Tseng and M. -H. Song, "Improving ESD robustness of stacked diodes with embedded SCR for RF applications in 65-nm CMOS," 2014 IEEE International Reliability Physics Symposium, 2014.
[18] J. Chen, C. Y. Lin, R. K. Chang, M. D. Ker, T. C. Tzeng, and T. C. Lin, “ESD protection design for high-speed applications in CMOS technology,” 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS), 2016, pp. 1-4.
[19] C. -T. Wang, T. -H. Tang and K. -C. Su, "Latch-up free ESD protection design with SCR structure in advanced CMOS technology," 2011 International Reliability Physics Symposium, 2011, pp. 4C.3.1-4C.3.4.
[20] Qiang Cui, S. Dong and Y. Han, "Investigation of waffle structure SCR for electro-static discharge (ESD) protection," 2012 IEEE International Conference on Electron Devices and Solid State Circuit (EDSSC), 2012, pp. 1-4.
[21] M. -H. Tsai, S. S. H. Hsu, F. -L. Hsueh, C. -P. Jou, S. Chen and M. -H. Song, "A Wideband Low Noise Amplifier With 4 kV HBM ESD Protection in 65 nm RF CMOS," in IEEE Microwave and Wireless Components Letters, vol. 19, no. 11, pp. 734-736, Nov. 2009.
[22] C. -Y. Lin, M. -L. Fan, M. -D. Ker, L. -W. Chu, J. -C. Tseng and M. -H. Song, "Improving ESD robustness of stacked diodes with embedded SCR for RF applications in 65-nm CMOS," 2014 IEEE International Reliability Physics Symposium, 2014.
[23] C. Lin and C. Chen, “Low-C ESD protection design with dual resistor-triggered SCRs in CMOS technology,” in IEEE Transactions on Device and Materials Reliability, vol. 18, no. 2, pp. 197-204, June 2018.
[24] C.-Y. Lin and R.-K. Chang, “Test structures of LASCR device for RF ESD protection in nanoscale CMOS process,” in Proc. IEEE International Conference on Microelectronic Test Structures, 2016, pp.100-103.
[25] M. -D. Ker and B. -J. Kuo, "Optimization of broadband RF performance and ESD robustness by π-model distributed ESD protection scheme," 2004 Electrical Overstress/Electrostatic Discharge Symposium, 2004.
[26] J. Li, K. Chatty, R. Gauthier, R. Mishra, and C. Russ, “Technology scaling of advanced bulk CMOS on-chip ESD protection down to the 32nm node,” in Proc. EOS/ESD Symp., 2009, pp. 69-75.
[27] C. T. Yeh, M. D. Ker, and Y. C. Liang, “Optimization on layout style of ESD protection diode for radio-frequency front-end and high-speed I/O interface circuits,” IEEE Trans. Device and Materials Reliability, vol. 10, no. 2, pp. 238-246, June 2010.
[28] 台灣半導體研究中心-高頻電路與天線量測實驗室
[29] S. Cao, J. -H. Chun, S. G. Beebe and R. W. Dutton, "ESD Design Strategies for High-Speed Digital and RF Circuits in Deeply Scaled Silicon Technologies," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, no. 9, pp. 2301-2311, Sept. 2010.
[30] Z. Piatek, W. A. Pleskacz and J. F. Kolodziejski, "Transmission Line Pulsing Tester For On-chip ESD Protection Testing," Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006., Gdynia, Poland, 2006, pp. 595-599.
[31] A. Shukla, R. Gamad and R. Raikwar, "Design of a CMOS Optical Receiver Front-End Using 0.18 μm Technology," Wireless Engineering and Technology, Vol. 4 No. 1, 2013, pp. 46-53.