第一顆電路為利用直接匹配技術之38 GHz二級功率放大器，透過傳輸線匹配網路達成輸出功率阻抗匹配、輸入共軛匹配之效果。當操作頻率為38 GHz且功率放大器的VG與VDD為-0.5 V與4 V時，其功率增益(Power gain)約為15.63 dB，飽和輸出功率Psat約為20.31 dBm，1-dB增益壓縮點之輸出功率(OP1dB)約為18.9 dBm，靜態電流約為81.5 mA，最大功率附加效率Peak PAE約為23.8 %，整體晶片佈局面積為1.2 mm × 0.8 mm。
第二顆電路為內具線性器之38 GHz二級功率放大器，線性器架構採用共源極組態。當操作頻率為38 GHz且VG為-0.5 V時，在線性器開啟狀態下(Vctrl = -0.2 V)，量測小訊號增益(S21)約為12.61 dB，輸入輸出反射損耗(S11、S22)分別為-7.81 dB與-13.23 dB，三階交互調變失真IMD3在-40 dBc的輸出功率約為14.12 dBm，整體晶片佈局面積為1.2 mm × 0.8 mm。
第三顆電路為內具線性器之38 GHz二級功率放大器，線性器架構採用共源極串級電阻組態。當操作頻率為38 GHz且VG為-0.5 V時，在線性器開啟狀態下(Vctrl = -0.3 V)，量測小訊號增益(S21)約為12.43 dB，輸入輸出反射損耗(S11、S22)分別為-9.3 dB與-12.71 dB，三階交互調變失真IMD3在-40 dBc的輸出功率約為13.55 dBm，整體晶片佈局面積為1.2 mm × 0.8 mm。
第四顆電路為內具線性器之38 GHz二級功率放大器，線性器架構採用疊接組態。當操作頻率為38 GHz且VG為-0.5 V時，在線性器開啟狀態下(Vctrl = -0.4 V)，量測小訊號增益(S21)約為11.56 dB，輸入輸出反射損耗(S11、S22)分別為-9.28 dB與-12.3 dB，三階交互調變失真IMD3在-40 dBc的輸出功率約為14.42 dBm，整體晶片佈局面積為1.2 mm × 0.8 mm。
第五顆電路為利用變壓器功率結合技術之38 GHz功率放大器，透過變壓器的功率結合與阻抗轉換特性來達成輸入共軛匹配與輸出功率匹配。當操作頻率為38 GHz且VG1為0.6 V時，功率增益(Power gain)約為15.07 dB，飽和輸出功率Psat約為19.98 dBm，1-dB增益壓縮點之輸出功率(OP1dB)約為15.05 dBm，靜態電流約為114 mA，最大功率附加效率Peak PAE約為29.42 %，整體晶片佈局面積為0.47 mm × 0.57 mm。
第六顆電路為利用變壓器電流結合技術之24 GHz功率放大器，採用二級功率放大器的方式以提升增益，接著使用變壓器電流結合技術來提高輸出功率。當操作頻率為24 GHz且VG1為1 V時，功率增益(Power gain)約為14.07 dB，飽和輸出功率Psat約為23.9 dBm，1-dB增益壓縮點之輸出功率(OP1dB)約為19.07 dBm，靜態電流約為354.06 mA，最大功率附加效率Peak PAE約為13 %，整體晶片佈局面積為0.99 mm × 0.91 mm。

The first circuit is a 38 GHz two stage power amplifier utilize transmission line matching network to achieve output matching and input impedance. At 38 GHz and the VG and VDD of the power amplifier operate in -0.5 V and 4 V, the power amplifier exhibits the power gain of 15.63 dB, the saturated output power of 20.31 dBm, the output power of 18.9 dBm at 1-dB compression point, the quiescent current of approximately 81.5 mA and the maximum power added efficiency of approximately 23.8%. The chip size is 1.2 mm × 0.8 mm.
The second circuit is a 38 GHz two stage power amplifier with built-in linearizer, the frame of the linearizer is using common source configuration. At 38 GHz and the VG and VDD of the power amplifier operate in -0.5 V and 4 V, when the linearizer is on (Vctrl = -0.2 V), the power amplifier exhibits the small signal gain (S21) of approximately 12.61 dB, the input and output reflection coefficient (S11, S22) of -7.81 dB and -13.23 dB, and the third-order intermodulation distortion (IMD3) can be maintained under -40 dBc when the output power less than 14.12 dBm. The chip size is 1.2 mm × 0.8 mm.
The third circuit is a 38 GHz two stage power amplifier with built-in linearizer, the frame of the linearizer is using common source cascade resistance configuration. At 38 GHz and the VG and VDD of the power amplifier operate in -0.5 V and 4 V, when the linearizer is on (Vctrl = -0.3 V), the power amplifier exhibits the small signal gain (S21) of approximately 12.43 dB, the input and output reflection coefficient (S11, S22) of -9.23 dB and -11.81 dB, and the third-order intermodulation distortion (IMD3) can be maintained under -40 dBc when the output power less than 13.55 dBm. The chip size is 1.2 mm × 0.8 mm.
The fourth circuit is a 38 GHz two stage power amplifier with built-in linearizer, the frame of the linearizer is using cascode configuration. At 38 GHz and the VG and VDD of the power amplifier operate in -0.5 V and 4 V, when the linearizer is on (Vctrl = -0.4 V), the power amplifier exhibits the small signal gain (S21) of approximately 11.56 dB, the input and output reflection coefficient (S11, S22) of -9.28 dB and -12.3 dB, and the third-order intermodulation distortion (IMD3) can be maintained under -40 dBc when the output power less than 14.42 dBm. The chip size is 1.2 mm × 0.8 mm.
The fifth circuit is a 38 GHz power amplifier with transformer power combining technique. To achieve input impedance matching, output power matching, we utilize the transformer to implement the impedance conversion and the power combining. At 38 GHz and the VG1 of the power amplifier operate in 0.6 V, the power amplifier exhibits the power gain of 15.07 dB, the saturated output power of 19.98 dBm, the output power of 15.05 dBm at 1-dB compression point, the quiescent current of approximately 114 mA and the maximum power added efficiency of approximately 29.42 %. The chip size is 0.47 mm × 0.57 mm.
The last circuit is a 24 GHz power amplifier with transformer power combining technique and current combining technique. To achieve high output power, we utilize the current combining technique. At 24 GHz and the VG1 of the power amplifier operate in 1 V, the power amplifier exhibits the power gain of 18.07 dB, the saturated output power of 23.9 dBm, the output power of 19.07 dBm at 1-dB compression point, the quiescent current of approximately 354.06 mA and the maximum power added efficiency of approximately 13.63 %. The chip size is 0.99 mm × 0.91 mm.

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