在半導體產業的蓬勃發展下，CMOS製程技術不斷地進步，使得積體電路的
尺寸越來越小且能在更低的供應電壓下操作，不論是晶片的面積或功率消耗都能
得到大幅地下降。因此，市場上對於體積輕薄且高效能的電子產品的需求變得越
來越高。在眾多的電子產品中，類比數位轉換器(Analog-to-Digital Converter, ADC)
都扮演著即其重要的角色，又尤其三角積分調變器(Delta-Sigma Modulator, DSM)
為相當熱門的研究對象。因為其獨特的超取樣技術以及雜訊移頻的特性，能有效
地降低類比元件非理想效應對電路效能的影響，並且能將信號頻帶內的雜訊大量
地移至高頻。三角積分調變器大多應用於高解析度且窄頻的音頻設備中。
本論文提出一個使用反相器基底積分器和相關電位移技術的二階雜訊移頻
SAR ADC，結合 DSM 優秀的雜訊移頻特性和雜訊移頻逐次逼近式類比數位轉換
器低功耗的優點，並藉由新提出的在輸出端採用相關電位移技術的反相器基底積
分器去改善以往運算放大器高功耗的缺點。此架構能在電路複雜度相當低的條件
下，實現低功耗且高解析度的類比數位轉換器。本研究使用 UMC 180nm 1P6M
CMOS 製程實現，供應電壓為 1.2V，取樣頻率為 3.072 MHz，頻寬為音頻應用的
20 kHz，量測所能達到的 SNDR 為 80.7 dB，總功率消耗為 103 μW，效能指標
FoMS為 163.5 dB。

With the vigorous development of the semiconductor industry, CMOS process
technology has continued to advance, making integrated circuits smaller and smaller and
able to operate at lower supply voltages. Both chip area and power consumption can be
greatly reduced Therefore, the market demand for electronic products that are light, thin
and high-performance is becoming higher and higher. In many electronic products,
analog-to-digital converters play an important role, and delta-sigma modulators are
particularly popular research objects. Because of its unique oversampling technology
and noise shaping characteristics, it can effectively reduce the impact of the non-ideal
effects of analog components on circuit performance, and can greatly shift the noise in
the signal band to high frequency. Delta-sigma modulators are mostly used in highresolution and narrow-band audio devices.
In this paper, a noise-shaping SAR ADC with an inverter-based integrator and
correlated level shifting technique is proposed, which combines the excellent noise
shaping characteristic of DSM and the advantage of low power consumption of noiseshaping successive approximation register analog-to digital converter (NS SAR ADC),
and the proposed inverter-based integrator with correlated level shifting at the output
can improve the high power consumption shortcoming of operational amplifier. This
architecture can realize low power consumption and high-resolution analog-to-digital
converter in low circuit complexity. This modulator was fabricated in a 0.18-μm 1P6M UMC CMOS process.. The measured SNDR is 83.4 dB, and the input DR is 83 dB in 20 kHz signal bandwidth with a clock frequency of 3.072 MHz. The power consumption of the proposed ΔΣ modulator is 103 μW in a 1.2-V supply voltage.

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