為了避免積體電路遭受靜電放電的破壞，靜電放電防護元件通常被設計在電路的輸入/輸出端。操作在順偏條件的二極體適合被作為靜電放電防護元件，因此靜電放電防護二極體被廣泛應用在高頻以及高壓電路，然而靜電放電防護二極體的寄生電容卻嚴重地影響電路的高頻特性，導致信號不斷流失，為了解決信號損失的問題，靜電放電防護二極體的寄生電容必須被最小化。然而，防護元件的寄生電容能夠縮小的範圍仍然有限，一個元件同時擁有足夠的靜電放電防護能力以及小的寄生電容是相當困難的。因此，本論文提出一種低損耗焊墊的結構，能夠有效降低防護元件對高頻的影響，透過LC共振原理使K/Ka-bands中的信號損失降至最低。低損耗焊墊搭配靜電放電防護雙二極體已被實現在0.18μm互補式金氧半製程中，從高頻量測中證實，所提出之結構的信號損失較傳統結構低了六至十倍。最後，藉由各項靜電放電耐受度測試驗證，所提出之結構能夠擁有足夠高的靜電放電防護能力。
由於二極體為單向導通元件，僅適合提供一個靜電放電的路徑，需額外加入靜電放電箝制電路才能提供電路完整的防護，然而靜電放電電流透過靜電放電箝制電路排放，通常需要較遠的距離。因此，本論文提出一種雙向導通的P型二極體結構，藉由PN接面的空乏區控制其通道，當靜電放電事件發生時，通道的空乏區將消失並排放靜電電流，而在正常工作中，空乏區應切斷其通道並有足夠低的漏電流，在高壓的應用中，橫向雙擴散電晶體經常被作為靜電放電防護元件，然而橫向雙擴散電晶體的結構複雜且不易設計，使得高壓操作中的靜電放電防護設計受到挑戰。二極體不但結構簡單且有足夠的靜電放電耐受度，因此本論文針對二極體的結構去進行改良，所提出的P型空乏二極體已被實現在0.50μm互補式金氧半製程中。從直流量測結果證實，在正常工作下P型空乏二極體有足夠低的漏電流，靜電放電耐受度測試中，透過通道排放靜電電流的想法是可行的但仍有需改進的地方。最後一章節的未來工作中將會提及一些改良的結構與想法。

The electrostatic discharge (ESD) protection devices are generally designed and employed near the input/output (I/O) pad to avoid the impact of ESD events. The diode operated under forward-biased condition is widely used as an ESD protection device in the integrated circuits (ICs). However, the parasitic capacitance of ESD protection diode seriously affects the high-frequency characteristics of the circuit and causes the signal to be lost. In order to solve the problem of signal loss, the parasitic capacitance of ESD protection diode must be minimized. However, the parasitic capacitance of protection device can be reduced in a limited range. It is difficult for a device to have sufficient ESD protection level and small parasitic capacitance at the same time. Therefore, this thesis proposes a structure of low-loss I/O pad that can effectively reduce the effect of ESD protection diode at high frequency. The signal loss at K/Ka-bands is minimized by the principle of LC resonance. The low-loss I/O pad with dual-diode ESD protection has been implemented in 0.18μm CMOS process. It is confirmed from the high-frequency measurement that the signal losses of proposed structures are 6~10 times lower than the traditional structure. Finally, it is verified by various ESD tests that the proposed structure has sufficiently high capability of ESD protection.
Since the diodes is a single-conducting device, it is only suitable for providing an ESD path. The circuit requires an additional power-rail ESD clamp to provide complete protection. However, the ESD current usually requires a long distance to discharge through a power-rail ESD clamp. Therefore, this thesis proposes a structure of bi-directional P-type diode, which is controlled by the depletion region of the PN-junction. When the ESD events occur, the depletion region of channel will disappear and discharge the ESD current. In the normal operation, the depletion region should close the channel and have a sufficiently low leakage current. For the high-voltage applications, the lateral double-diffused MOS (LDMOS) is often used as the ESD protection device. However, the structure of LDMOS is complex and difficult to design. The ESD protection design is challenged in high-voltage operation. The structure of diode is simple and it has sufficient ESD protection level. Therefore, this thesis aims to improve the structure of diode. The P-type depletion diodes have been fabricated in 0.50μm CMOS process. It is confirmed from the DC measurement that the P-type depletion diodes have a sufficiently low leakage current under the normal operation. From the ESD tests, the idea of discharging ESD current through the channel is feasible but there is still room for improvement. Some improved structures and ideas will be mentioned in the future work of the final chapter.

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