本論文旨在研究應用於高速積體電路之全晶片靜電放電防護設計，在CMOS製程下實作，以低電容元件搭配分散式電路的設計，並與既有二極體及電晶體元件的設計相比較。
隨著內部電路的操作頻率不斷提升，寄生電容造成的訊號損耗嚴重影響電路高頻性能，本篇論文利用兩級分散式電路架構的方式，將單級的防護元件以小尺寸分散至兩級來設計防護電路，以降低每級的元件寄生電容，並在兩級之間以匹配元件降低訊號通過時的損耗，形成π型架構的設計。傳統的π型架構設計使用的是二極體或電晶體元件，本論文提出利用其他低電容矽控整流器元件如堆疊二極體內嵌矽控整流器 (SDSCR) 及電阻觸發式矽控整流器 (RTSCR) 搭配π型架構，組成π-SDSCR與π-RTSCR，來與π型連接的傳統元件進行比較。由實驗結果可知，在20GHz時，創新設計π-SDSCR在單位插入損耗 (S21) 下所達到的二次崩潰電流 (It2) 為傳統設計的1.76倍，π-RTSCR則為傳統設計的1.62倍，相較於傳統架構，本文提出的設計具備更高的ESD防護能力及更低的寄生電容，更適用於高速電路。
最後，為了驗證與比較防護電路的性能，本論文也設計了一應用於高速的轉阻放大器 (Trans-impedance amplifier, TIA)，分別搭配傳統π型二極體設計與本論文所提出的防護電路，並進行電路的量測，驗證實際的防護效果及對電路性能的影響。由實驗結果可知，創新設計與傳統設計都能為TIA電路提供4kV的HBM ESD 耐受度，且π-SDSCR在17GHz時的插入損耗僅傳統設計的0.83倍，π-RTSCR則為傳統設計的0.9倍，顯示創新設計在提供足夠ESD耐受度的同時，對電路高頻性能影響更低。

This thesis is to study a whole-chip electrostatic discharge (ESD) protection design for high-speed circuits. In CMOS process, the low-capacitance device is designed with distributed circuit in comparison with traditional design by diode and MOS.
As the operating frequency of the internal circuit increases, the signal loss caused by parasitic capacitance seriously affects the high-frequency performance of the circuit. A two-stage distributed circuit architecture is used in this thesis to divide a single-stage protection device into two stages in a small size which can reduce the parasitic capacitance of the device in each stage. The matching element is added between two stages and formed π-structure to reduce the signal loss. Diode or MOS is used in traditional π-model design. This thesis proposes to use other innovative low-capacitance silicon-controlled rectifier (SCR) such as stacked diodes with embedded silicon-controlled rectifier (SDSCR) and resistor-triggered SCR (RTSCR) with the π-model to compare with the π-connected traditional devices. From the experiment result, the secondary breakdown current (It2) provided by proposed π-SDSCR per unit insertion loss (S21) at 20GHz is 1.76 times higher than that of the traditional design. That value provided by proposed π-RTSCR is 1.62 times higher than that of the traditional design. As compare with traditional structure, proposed designs have higher ESD protection ability and lower parasitic capacitance which are more suitable for high-speed circuits.
In order to verify and compare the performance of the protection circuits, this thesis designed a high-speed trans-impedance amplifier (TIA), which has added the traditional π-diode and the proposed π-SCR in this paper as ESD protection. The circuits were measured to verify the protection ability and the influence on the circuit performance. From the experiment result, both traditional and proposed designs provide 4kV HBM ESD robustness for the TIA circuit. However, the degradation of insertion loss (ΔS21) of TIA with π-SDSCR at 17GHz is only 0.83 times of that of TIA with traditional design. The value of TIA with π-RTSCR is 0.9 times of that of TIA with traditional design. It shows that as compare with traditional structure, proposed designs have lower impact on the high frequency performance of the circuit, while also providing sufficient ESD tolerance.

[1] S. H. Voldman, ESD Physics and Devices. New York: Wiley, 2005.
[2] O. Semenov et al., ESD Protection Devices and Circuit Design for Advanced CMOS Technologies. Amsterdam: Springer, 2008.
[3] T. Lim et al., “Geometrical impact on RF performances of broadband ESD self-protected transmission line in advanced CMOS technologies,” in Proc. IEEE International Integrated Reliability Workshop, Oct. 2012, pp. 14-18.
[4] ESD Association and JEDEC Solid State Technology Association, “Human body model (HBM) - component level,” ANSI/ESDA/JEDEC JS-001-2017, 2017.
[5] Microelectronics Test Method Standard MIL-STD-883D Method 301 5.7, “Electrostatic discharge sensitivity classification,” US Department of Defense, 1991.
[6] Industry Council on ESD Target Levels, “White Paper 1: A case for lowering component level HBM/MM ESD specifications and requirements,” June. 2018.
[7] E. Grund et al., “A new CDM discharge head for increased repeatability and testing small pitch packages,” in Proc. EOS/ESD Symposium, 2018.
[8] ESD Association and JEDEC Solid State Technology Association, “Charged device model (CDM) -component level,” ANSI/ESDA/JEDEC JS-002-2014, 2014.
[9] W.-Y. Chen et al., “Diode-triggered silicon-controlled rectifier with reduced voltage overshoot for CDM ESD protection,” IEEE Transactions on Device and Material Reliability, vol. 12, no. 1, pp. 10-14, Mar. 2012.
[10] Industry Council on ESD Target Levels, “White Paper 2: A case for lowering component level CDM ESD specifications and requirements,” May. 2021.
[11] G. Boselli et al., “Analysis of ESD protection components in 65-nm CMOS technology: Scaling perspective and impact on ESD design windows,” in Proc. EOS/ESD Symposium, 2005, pp. 43-52.
[12] A. Amerasekera and C. Duvvury, ESD in Silicon Integrated Circuits. New York: Wiley, 1995.
[13] R. Wong et al., “Networking industry trends in ESD protection for high speed IOs,” 2013 IEEE 10th International Conference on ASIC, 2013, pp. 1-4.
[14] S. Cao et al., “ESD design strategies for high-speed digital and RF circuits in deeply scaled silicon technologies,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, no. 9, pp. 2301-2311, Sept. 2010.
[15] Q. Cui et al., “High-Robustness and Low-Capacitance Silicon-Controlled Rectifier for High-Speed I/O ESD Protection,” in IEEE Electron Device Letters, vol. 34, no. 2, pp. 178-180, Feb. 2013.
[16] J. Chen et al., “ESD protection design for high-speed applications in CMOS technology,” 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS), 2016, pp. 1-4.
[17] A. Y. Ginawi et al., “Investigation of diode triggered silicon control rectifier turn-on time during ESD events,” in Proc. IEEE System-on-Chip Conference, 2017, pp. 5-8.
[18] M.-D. Ker and K.-C. Hsu, “Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits,” IEEE Transactions on Devices and Materials Reliability, vol. 5, no. 2, pp. 235-249, Jun. 2005.
[19] C. Yeh et al., “Optimization on Layout Style of ESD Protection Diode for Radio-Frequency Front-End and High-Speed I/O Interface Circuits,” in IEEE Transactions on Device and Materials Reliability, vol. 10, no. 2, pp. 238-246, June 2010.
[20] C. Lin et al., “Improving ESD robustness of stacked diodes with embedded SCR for RF applications in 65-nm CMOS,” 2014 IEEE International Reliability Physics Symposium, 2014, pp. EL.1.1-EL.1.4.
[21] C. Lin and C. Chen, “Low-C ESD protection design with dual resistor-triggered SCRs in CMOS technology,” in IEEE Transactions on Device and Materials Reliability, vol. 18, no. 2, pp. 197-204, June 2018.
[22] M.-D. Ker et al., “Optimization of broadband RF performance and ESD robustness by -model distributed ESD protection scheme,” Journal of Electrostatics, vol. 64, no. 2, pp. 80-87, Feb. 2006.
[23] A. Dong et al., “Distributed ESD protection network for millimetre-wave RF applications,” IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, 2018.
[24] T. Lim et al., “Generic electrostatic discharges protection solutions for RF and millimeter-wave applications,” IEEE Transactions on Microwave Theory and Techniques, vol. 63, no. 11, pp. 3747-3759, Nov. 2015.
[25] Ming-Dou Ker and K. -. Lin, “Overview on electrostatic discharge protection designs for mixed-voltage I/O interfaces: design concept and circuit implementations,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 53, no. 2, pp. 235-246, Feb. 2006.
[26] M.-D. Ker et al., “Overview on ESD protection designs of low-parasitic capacitance for RF ICs in CMOS technologies,” IEEE Transactions on Device and Materials Reliability, vol. 11, no. 2, pp. 207-218, Jun. 2011.
[27] 台灣半導體研究中心-高頻電路與天線量測實驗室
[28] S. Cao et al., “ESD design strategies for high-speed digital and RF circuits in deeply scaled silicon technologies,” IEEE Transactions on Circuits and Systems, Part I: Regular Papers, vol. 57, no. 9, pp. 2301-2311, Sep. 2010.
[29] K. Shrier et al., “Transmission line pulse test methods, test techniques and characterization of low capacitance voltage suppression device for system level electrostatic discharge compliance,” in Proc. EOS/ESD Symposium, 2004.
[30] 國立陽明交通大學電子工程學系暨電子研究所-積體電路及系統實驗室
[31] Y. Zhou et al., “A new method to evaluate effectiveness of CDM ESD protection,” Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2010, 2010, pp. 1-8.
[32] J. Jin and S. S. H. Hsu, “A 40-Gb/s transimpedance amplifier in 0.18-m CMOS Technology,” in IEEE Journal of Solid-State Circuits, vol. 43, no. 6, pp. 1449-1457, June 2008
[33] P. Sinsoontornpong and A. Worapishet, "π-peaking shunt-feedback transimpedance amplifier with bandwidth enhancement," 2012 IEEE International Conference on Electron Devices and Solid State Circuit (EDSSC), 2012, pp. 1-4
[34] N. Jack and E. Rosenbaum, “ESD protection for high-speed receiver circuits,” in Proc. IEEE International Reliability Physics Symposium, 2010, pp. 835-840.
[35] I. G. López et al., "A 50 Gb/s TIA in 0.25µm SiGe:C BiCMOS in folded cascode architecture with pnp HBTs," 2016 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 2016, pp. 9-12.
[36] J. Jin and S. S. H. Hsu, "A 75-dB⋅Ω 10-Gb/s Transimpedance Amplifier in 0.18-µm CMOS Technology," in IEEE Photonics Technology Letters, vol. 20, no. 24, pp. 2177-2179, Dec.15, 2008.
[37] I. García López et al., "A DC-75-GHz Bandwidth and 54 dBΩ Gain TIA With 10.9 pA/√Hz in 130-nm SiGe:C BiCMOS," in IEEE Microwave and Wireless Components Letters, vol. 28, no. 1, pp. 61-63, Jan. 2018.
[38] S. G. Kim et al., "A 40-GHz Mirrored-Cascode Differential Transimpedance Amplifier in 65-nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 54, no. 5, pp. 1468-1474, May 2019.
[39] P. Peng et al., “Low-Capacitance SCR for On-Chip ESD Protection with High CDM Tolerance in 7nm Bulk FinFET Technology, ” 2019 41st Annual EOS/ESD Symposium (EOS/ESD), 2019, pp. 1-5