研究生: |
張國煌 Kuo-Huang Chang |
---|---|
論文名稱: |
32位元小面積之嵌入式AES的FPGA設計與影像應用 A 32-bit Low Area Embedded AES FPGA Design for Image Application |
指導教授: |
黃奇武
Huang, Chi-Wu 張吉正 Chang, Chi-Jeng |
學位類別: |
碩士 Master |
系所名稱: |
電機工程學系 Department of Electrical Engineering |
論文出版年: | 2009 |
畢業學年度: | 97 |
語文別: | 中文 |
論文頁數: | 65 |
中文關鍵詞: | 高等加密標準 、現場可程式化閘陣列 、影像處理 |
英文關鍵詞: | AES, FPGA, Embedded System, MicroBlaze |
論文種類: | 學術論文 |
相關次數: | 點閱:233 下載:6 |
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高等加密標準(Advanced Encryption Standard, AES)硬體實現在現場可程式化閘陣列(FPGA)與特殊用途積體電路(ASIC)已經被很廣泛的討論,尤其是如何達到數十億產率的議題;然而在嵌入式硬體的應用上,低產率與小面積的設計在近幾年也開始被研究。
本研究提出一個小面積的硬體電路,採用32位元的架構來實現AES-128的規格,其中包含2組移位暫存器(Shift Register)來完成移列轉換(ShiftRow)的動作;並利用晶片內建的Block RAM來放置整合資料,完成位元組替換(SubByte)與混行運算(MixColumn)的動作;而以軟體來取代硬體的金鑰擴展(KeyExpansion),來節省電路面積。透過上述所提出的方式在FPGA上所完成的實驗數據,其資源消耗為110個Slice、速度可達到75Mhz(每秒可處理29張640×480大小的彩色影像),是在目前文獻中面積最小的設計。
為實現影像加解密的應用,本研究分別使用兩種方式來與上述32位元AES核心電路整合,其一為結合嵌入式系統與IP core的架構,屬於軟體與硬體的搭配;另一為只用硬體描述語言(HDL)來實現,較偏向硬體電路來控制。
Advance Encryption Standard (AES) hardware implementation in FPGA and ASIC have been intensely discussed, especially in high-throughput of Giga bit per second (Gbps). However, lower throughput and area designs have also been investigated in the recent years for embedded hardware applications.
This paper presents a 32-bit AES implementation with a speed of 75MHz (29 640x480 frames per second) and low area of 110 slices, which is the smallest design among literature reports. There are two Shift-Registers for ShiftRow; a built-in Block RAM for SubByte and MixColumn; KeyExpansion utilizing software instead of hardware.
In order to realize image encryption/decryption, we combine the 32-bit AES with two types of implements. First, the Embedded System with a MicroBlaze core which uses software and hardware codesign. Second, using HDL hardware description language, which is mainly a hardware implementation.
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