簡易檢索 / 詳目顯示

研究生: 張國煌
Kuo-Huang Chang
論文名稱: 32位元小面積之嵌入式AES的FPGA設計與影像應用
A 32-bit Low Area Embedded AES FPGA Design for Image Application
指導教授: 黃奇武
Huang, Chi-Wu
張吉正
Chang, Chi-Jeng
學位類別: 碩士
Master
系所名稱: 電機工程學系
Department of Electrical Engineering
論文出版年: 2009
畢業學年度: 97
語文別: 中文
論文頁數: 65
中文關鍵詞: 高等加密標準現場可程式化閘陣列影像處理
英文關鍵詞: AES, FPGA, Embedded System, MicroBlaze
論文種類: 學術論文
相關次數: 點閱:233下載:6
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • 高等加密標準(Advanced Encryption Standard, AES)硬體實現在現場可程式化閘陣列(FPGA)與特殊用途積體電路(ASIC)已經被很廣泛的討論,尤其是如何達到數十億產率的議題;然而在嵌入式硬體的應用上,低產率與小面積的設計在近幾年也開始被研究。
      本研究提出一個小面積的硬體電路,採用32位元的架構來實現AES-128的規格,其中包含2組移位暫存器(Shift Register)來完成移列轉換(ShiftRow)的動作;並利用晶片內建的Block RAM來放置整合資料,完成位元組替換(SubByte)與混行運算(MixColumn)的動作;而以軟體來取代硬體的金鑰擴展(KeyExpansion),來節省電路面積。透過上述所提出的方式在FPGA上所完成的實驗數據,其資源消耗為110個Slice、速度可達到75Mhz(每秒可處理29張640×480大小的彩色影像),是在目前文獻中面積最小的設計。
      為實現影像加解密的應用,本研究分別使用兩種方式來與上述32位元AES核心電路整合,其一為結合嵌入式系統與IP core的架構,屬於軟體與硬體的搭配;另一為只用硬體描述語言(HDL)來實現,較偏向硬體電路來控制。

    Advance Encryption Standard (AES) hardware implementation in FPGA and ASIC have been intensely discussed, especially in high-throughput of Giga bit per second (Gbps). However, lower throughput and area designs have also been investigated in the recent years for embedded hardware applications.
      This paper presents a 32-bit AES implementation with a speed of 75MHz (29 640x480 frames per second) and low area of 110 slices, which is the smallest design among literature reports. There are two Shift-Registers for ShiftRow; a built-in Block RAM for SubByte and MixColumn; KeyExpansion utilizing software instead of hardware.
      In order to realize image encryption/decryption, we combine the 32-bit AES with two types of implements. First, the Embedded System with a MicroBlaze core which uses software and hardware codesign. Second, using HDL hardware description language, which is mainly a hardware implementation.

    摘  要 i ABSTRACT ii 誌  謝 iii 目  錄 iv 表 目 錄 vi 圖 目 錄 vii 第一章  緒論 1 1.1  研究背景 1 1.2  研究動機 4 1.3  研究目的 5 1.4  研究步驟 6 第二章  演算法及文獻探討 7 2.1  高等加密標準演算法介紹 7 2.1.1 演算法流程 7 2.1.2 位元組替換與反位元組替換 8 2.1.3 移列轉換與反移列轉換 10 2.1.4 混行運算與反混行運算 10 2.1.5 回合金鑰加法運算 11 2.2  文獻探討 13 2.2.1 Pawel Chodowiec架構 13 2.2.2 Gael Rouvroy架構 15 第三章  硬體架構與單元設計 17 3.1  小面積32位元AES電路架構 17 3.2  嵌入式系統架構 20 3.2.1 32位元AES IP元件之建立 21 3.2.2 系統組織規劃 22 3.2.3 軟體介面與流程規劃 23 3.3  硬體控制式架構 30 3.3.1 Parallel Port控制器設計 30 3.3.2 SRAM控制器設計 34 3.3.3 VGA控制器設計 40 3.3.4 FIFO控制器設計 43 3.3.5 AES控制器設計 47 3.3.6 電腦端收發與操作介面規劃 49 第四章  實驗成果分析 52 4.1 驗證平台規劃 52 4.2 32位元AES電路效能比較 54 4.3 嵌入式系統實驗成果 56 4.4 硬體控制式實驗成果 58 第五章  結論與未來展望 60 參考文獻 61 自  傳 63 學術成就 65

    [1] NIST. Announcing the advanced encryption standard (AES), FIPS 197. Technical report, National Institute of Standards and Technology, November 2001.
    [2] T. Good and M. Benaissa “Pipelined AES on FPGA with support for feedback modes (in a multi-channel environment),” in the Institution of Engineering and Technology, vol. 1, no. 1, pp. 1–10, April 2007.
    [3] A. Hodjat, “Area-Throughput Trade-Offs for Fully Pipelined 30 to 70 Gbits/s AES Processors,” IEEE Trans. Computers, vol. 55, no. 4, pp. 366–372, April 2006.
    [4] A. Hodjat and I. Verbauwhede, “Interfacing a high speed crypto accelerator to an embedded cpu,” In Proc. 38th Asilomar Conference on Signals, Systems, and Computers, vol. 1, pp. 488–492, November 2004.
    [5] Chi-Wu Huang, Chi-Jeng Chang, Mao-Yuan Lin, and Hung-Yun Tai, “The FPGA Implementation of 128-bits AES Algorithm Based on Four 32-bits Parallel Operation,” ISDPE 2007, pp. 462–464, November 2007.
    [6] Ricardo Chaves, Georgi Kuzmanov, Stamatis Vassiliadis, and Leonel Sousa, “Reconfigurable Memory Based AES Co-Processor,” International Parallel and Distributed Processing Symposium, April 2006.
    [7] Tim Good, “Very Small FPGA Application-Specific Instruction Processor for AES,” IEEE Trans. Circuits and Systems—I: Regular Papers, vol. 53, no. 7, July 2006.
    [8] Pawel Chodowiec and Kris Gaj, “Very Compact FPGA Implementation of the AES Algorithm”, Cryptographic Hardware and Embedded Systems, vol. 2779, pp. 319–333, September 2003.
    [9] G. Rouvroy, F.-X. Standaert, J.-J. Quisquater and J.-D. Legat, “Compact and efficient encryption/decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications”, In Proc. IEEE Int. Conf. on Inf. Tech.: Coding and Computing, vol. 2, pp. 583–587, Las Vegas, NV, USA, April. 2004.
    [10] Chi-Wu Huang, Chi-Jeng Chang, Mao-Yuan Lin, Hung-Yun Tai, “Compact FPGA Implementation of 32-bits AES Algorithm Using Block RAM,” TECON 2007, pp. 1–4, Oct.30-Nov.2 2007.
    [11] X. Zhang and K. K.Parhi “High Speed VLSI Architectures for the AES Algorithm,” IEEE Trans. VLSI Systems, vol. 12, no. 9, September 2004.
    [12] Chih-Peng Fan, Jun-Kui Hwang “Implementations of High Throughput Sequential and Fully Pipelined AES Processors on FPGA,” In Proc. International Symposium on Intelligent Signal Processing and Communication Systems, Nov.28-Dec.1, 2007 Xiamen, China.
    [13] J. Wolkerstorfer, E. Oswald, M, Lamberger, “An ASIC Implementation of the AES SBoxes,” CT-RSA 2002, LNCS 2271, pp-67-78, 2002.
    [14] Hannes Brunner, Andreas Curiger, and Max Hofstetter, “”On Computing Multiplicative Inverses in GF (2m),” IEEE Trans. Computers, vol. 42, no. 8, August 1993.
    [15] Jyh-Huei Guo and Chin-Liang Wang,” Systolic Array Implementation of Euclids Algorithm for Inversion and Division in GF (2m),” IEEE Trans. Computers, vol. 47, no. 10, October 1998.
    [16] William Stallings, Cryptography and Network Security: Principles and Practice. Prentice Hall, 1999.

    下載圖示
    QR CODE