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研究生: 張文亮
論文名稱: 鐵酸鉍摻雜錳與二氧化鋯絕緣層電容器之電特性分析
Effect of annealing temperature and Ar/O2 ratio on Mn-doped BiFeO3 thin films and capacitors fabricated by RF magnetron sputtering
指導教授: 劉傳璽
Liu, Chuan-Hsi
阮弼群
Juan, Pi-Chun
學位類別: 碩士
Master
系所名稱: 機電工程學系
Department of Mechatronic Engineering
論文出版年: 2012
畢業學年度: 100
語文別: 中文
論文頁數: 67
中文關鍵詞: BFO記憶視窗MFIS電容薄膜
英文關鍵詞: BFO, Memory window, MFIS capacitor, Thin film
論文種類: 學術論文
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  • 在此論文中,利用射頻磁控濺鍍法製造出金屬-鐵電層-絕緣層-半導體的電容,鐵電層為鐵酸鉍摻雜錳及絕緣層為二氧化鋯所完成的 MFIS結構電容。二氧化鋯絕緣層厚度為20,40與60奈米。摻雜錳之鐵電層厚度為250 nm。BFO使用射頻濺鍍製成,錳使用直流系統摻雜,直流系統功率為5 W、10 W、15 W。濺鍍時氬氧比為30/2、30/3、30/6 sccm/sccm。用快速熱退火方式使鐵電薄膜產生結晶,熱退火在充滿氮氣的環境下,溫度升溫到500℃、600℃、或700℃。使用鋁做為上電極,再做PMA退火於400℃,於氮氣環境下持溫30秒。
    結果發現,電容器經過熱退火,其電容器的記憶視窗會因為熱退火的溫度愈高,記憶視窗愈大。然而高退火溫度也會導致氧化鋯絕緣層會產生結晶,而增加漏電流。因此只要考慮熱退火的溫度,並在MFIS電容器的記憶視窗寬度與漏電流兩者間取得一平衡值。甚至此實驗結果也顯示出鐵電記憶體的表現可以藉由摻雜錳與氧到BFO薄膜做改善。文獻指出因為錳的直徑(0.072奈米)與鐵的直徑(0.069奈米)很接近,所以錳可以作為取代鐵的元素。因跳躍電子關係,鐵會填補氧空缺。在退火溫度600℃且氬氧比是30/6 sccm/sccm時,其最大的記憶視窗是3.04 V。

    In this work, metal-ferroelectric-insulator-semiconductor (MFIS) capacitors with Mn-doped BiFeO3 (BFO) as the ferroelectric layer and ZrO2 as the insulating layer have been fabricated by radio frequency (RF) magnetron sputtering technique. The thickness of the high-k ZrO2 layer was 20, 40, or 60 nm. The 250-nm-thick Mn-doped BFO ferroelectric layer was deposited by co-sputtering method, in which the RF and DC powers were used for BFO and Mn targets, respectively. The DC power (5, 10, or 15 W utilized in this study) can be used to adjust the Mn doping concentration in the BFO films. Moreover, during the co-sputtering process, the Ar/O2 gas ratio (30/2, 30/3, or 30/6 sccm/sccm) was also varied to control the oxygen content. In order to crystallize the ferroelectric films, rapid thermal annealing (RTA) was carried out in pure N2 at 500, 600, or 700℃. Aluminum was used as the top electrode. A post-metallization annealing (PMA) was performed at 400℃ in N2 for 30 s.
    It is found that the size of memory window of MFIS capacitors increases with increasing RTA temperature. However, a high RTA temperature may also cause the crystallization of ZrO2 layers, increasing the leakage current. Therefore, as long as the RTA temperature is concerned, there is a tradeoff between memory window and leakage current of MFIS capacitors. Moreover, the experimental results show that the ferroelectric memory performance can be improved through Mn doping and O2 incorporation in the BFO films. It has been reported that Mn is a substitution element for BFO films because the radius (0.072 nm) of Mn3+ ions was similar to that of Fe3+ ions (0.069 nm). Therefore, the hopping of electrons between Fe2+ and Fe3+ when oxygen vacancies are present is proposed to be responsible for the leakage current. The maximum memory window of 3.04 V was obtained from a sweep voltage of 8 V when the annealing temperature was 600 ℃ and Ar/O2 ratio was 5.

    第一章 緒論 1 1-1 半導體技術 1 1-2 鐵電材料 4 1-3 研究動機 5 第二章 文獻探討 7 2-1 CMOS記憶體 7 2-2 FRAM 8 2-3 高介電係數材料 11 2-4 鐵電材料之特性 12 2-5 摻雜理論 16 2-6 MFIS結構理論 21 2-7 界面層效應 23 第三章 實驗設計 25 3-1 薄膜沉積簡介 26 3-1-1 濺鍍沉積 30 3-1-2 直流濺鍍 32 3-1-3 射頻濺鍍 33 3-2 物性量測機台簡介 34 3-2-1 穿透式電子顯微鏡 34 3-2-2 X射線光電子能譜儀 35 3-3 電容器的製備 36 3-3-1 薄膜成長 36 3-3-2 電極的製作 37 3-3-3 電容器的量測 38 第四章 結果與討論 41 4-1 基本電性量測分析 41 4-2電容-電壓(C-V)特性量測 42 4-2-1 不同的退火溫度之C-V電性分析 42 4-2-2 不同的絕緣層厚度之C-V電性分析 45 4-2-3 不同的摻雜功率之C-V電性分析 48 4-2-4 不同的氬氧比例之C-V電性分析 51 4-3電流-電壓(I-V)特性量測 54 4-3-1 不同的退火溫度之I-V電性分析 54 4-3-2 不同的絕緣層厚度之I-V電性分析 56 4-3-3 不同的摻雜功率之I-V電性分析 58 4-3-4 不同的氬氧比例之I-V電性分析 60 第五章 結論與未來展望 63 5-1 結論 63 5-2 未來展望 64 參考文獻 65

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