本論文提出了應用於音頻數位類比轉換器的24位元低成本、高效率插值濾波器和三角積分調變器。在插值濾波器中，我們採用凱薩窗函數來設計具有較少硬體的線性相位半頻帶有限脈衝響應濾波器，除了能有相對較少的濾波器階數外，還能加大頻帶外的阻帶衰減率，並抑制鏡像雜訊。此外，利用多工器來減少大量的加法器，改善使用多相位折疊架構具有加法器數量與濾波器階數成正比的缺點。在三角積分調變器中，使用2+2 SMASH架構來確保高階三角積分調變器的穩定。採用訊號處理電路來節省輸入至第二級電路前的多位元減法器，並於第二級採用硬體成本較低的量化誤差回授架構，改善SMASH架構在硬體成本上的缺點。
　　本研究提出的電路架構使用TSMC 0.18-um 1P6M CMOS技術實現，總耗費的核心面積為0.35 mm2。在24 kHz的頻帶下，測得的SNR為143.91 dB，且在1.8 V的電源電壓下，測得功率消耗為3.14 mW。此外，利用Altera Cyclone IV GX型號的FPGA開發板進行驗證，從量測的結果顯示，在24 kHz的頻帶下，測得的效能與post-sim相同。總共使用的邏輯數目(LEs)為3697。在1.2 V的電源電壓下，測得的功率消耗為0.93 mW。

This paper presents a 24-bit, low-cost, high-efficiency interpolation filter and delta-sigma modulator for audio digital-to-analog converters (DACs). In the interpolation filter, we employ a Kaiser window function to design a linear-phase, half-band finite impulse response (FIR) filter with reduced hardware complexity. This design not only reduces the number of filter stages but also increases the stopband attenuation beyond the passband, effectively suppressing image noise. Additionally, we utilize multiplexers to reduce a large number of adders, addressing the drawback of the polyphaser-folded architecture where the number of adders is proportional to the filter stages. In the delta-sigma modulator, a 2+2 SMASH architecture is used to ensure stability for higher-order delta-sigma modulator. Signal processing circuits are employed to save multi-bit subtractors before the second stage, and a error feedback structure with lower hardware cost is implemented in the second stage to address the hardware cost limitation of the SMASH architecture.
　　The proposed architecture in this study was implemented using TSMC 0.18-um 1P6M CMOS technology, with a total core area of 0.35 mm2. In the 24 kHz bandwidth, the measured SNR was 143.91 dB, and the power consumption was measured at 3.14 mW with a supply voltage of 1.8 V. Furthermore, verification was performed using an Altera Cyclone IV GX model FPGA development board, and the measured performance in the 24 kHz bandwidth matched the post-simulation results. The total number of used logic elements (LEs) was 3697. At a supply voltage of 1.2 V, the measured power consumption was 0.93 mW.

[1] Z. Kulka and P. Woszczek,“Implementation of digital sigma-delta modulators for high-resolution audio digital-to-analog converters based on field programmable gate array,”Arch. Acoust., vol. 33, no. 1, pp. 93-101, 2008.
[2] S. Pavan, R. Schreier, and G. C. Temes, “Understanding Delta-Sigma Data Converters,” 2nd ed. Piscataway, NJ, USA: IEEE Press, 2017.
[3] N. B. Ameur, M. Soyah, N. Masmoudi and M. Loulou, “FPGA implementation of polyphase decomposed FIR filters for interpolation used in Δ-Σ audio DAC,” IEEE International Conference on Signals, Circuits and Systems (SCS), 2009, pp. 1-4.
[4] B. Luo, Y. Zhao and Z. Wang, “An Area-Efficient Interpolator Applied in Audio Σ Δ DAC,” IEEE Conference on Signal-Image Technologies and Internet-Based System, 2007, pp. 538-541.
[5] Y. Liu, J. Gao and X. Yang, “24-bit low-power low-cost digital audio sigma-delta DAC,” IEEE Tsinghua Science and Technology, vol. 16, no. 1, pp. 74-82, Feb. 2011.
[6] Z. Yu, Y. Fan and G. Lv, “An FPGA-based digital class-D amplifier with power supply error correction,” IEEE Conference on Industrial Electronics and Applications, 2014, pp. 1356-1360
[7] X. Li and A. Lee, “An FPGA implemented 24-bit audio DAC with 1-bit sigma-delta modulator,” IEEE Asia Pacific Conference on Circuits and Systems, 2010, pp. 768-771.
[8] J. Noh and C. Yoo, “Interpolated Digital Delta-Sigma Modulator for Audio D/A Converter ”, Korea Science, Journal of IEIE, vol. 49, no. 11, Nov. 2012.
[9] J. Zhao, X. Wu and M. Zhao, “A digital front-end of 16-bit audio delta-sigma DAC with improved CSE method and novel DWA,” IEEE International NEWCAS Conference, 2012, pp. 273-276.
[10] S. Liu, W. Jiang, and M. Zhang, “Dual-channel multiplexing technology and its realization in interpolation filter in stereo audio SigmaDelta DAC,” Analog Integr Circ Sig Process, vol. 81, no. 2, pp. 487–494, 2014.
[11] X. Huang, Y. Han and L. Chen, “The Design and FPGA Verification of a General Structure, Area-optimized Interpolation Filter Used in /spl Delta/-/spl Sigma/ DAC,” IEEE International Conference on Solid-State and Integrated Circuit Technology Proceedings, 2006, pp. 2111-2113.
[12] J. Li, X. -B. Wu and J. -C. Zhao, “An improved area-efficient design method for interpolation filter of Sigma-Delta audio DAC,” IEEE International Conference on Solid-State and Integrated Circuit Technology, 2010, pp. 327-329.
[13] T. Memon, et al., “Power-Area-Performance Characteristics of FPGA based sigma-delta modulated FIR Filters,” J. Sign Process Syst., vol. 70, pp. 275-288, 2013.
[14] S. Raj and A. Shaji, “Design and implementation of reconfigurable digital filter bank for hearing aid,” IEEE International Conference on Emerging Technological Trends (ICETT), 2016, pp. 1-6.
[15] K. Lee et al., “A 0.8 V, 2.6 mW, 88 dB Dual-Channel Audio Delta-Sigma D/A Converter with Headphone Driver,” IEEE J. Solid-State Circuits, vol. 44, no. 3, pp. 916-927, Mar. 2009.
[16] Sonika, D. D. Neema, and R. N. Patel, “Design and implementation of sigma-delta digital to analog converter,” Sādhanā, vol. 43, no. 6, pp. 1-11, June. 2018.
[17] V. Puidokas and A. J. Marcinkevičius, “Research on Characteristics of Audio DAC Sigma-Delta Modulator on Field Programmable Gate Array,” Elektronika Ir Elektrotechnika, vol. 85, no. 5, pp. 97-100, May. 2008.
[18] S. Liu, W. Jiang, and M. Zhang, “Dual-channel multiplexing technology and its realization in interpolation filter in stereo audio sigma-delta DAC,” Analog Integrated Circuits and Signal Processing, vol. 81, no. 2, pp. 487-494, Nov. 2014.
[19] M. Annovazzi, V. Colonna, G. Gandolfi, F. Stefani, and A. Baschirotto, “A low-power 98-dB multibit audio DAC in a standard 3.3-V 0.35-um CMOS technology,” IEEE J. Solid-State Circuits, vol. 37, no. 7, pp. 825-834, Jul. 2002.
[20] D. Schlichthärle, “Digital Filters : Basics and Design, ” Berlin, Germany: Springer, 2011.
[21] P. Li, W. Xi, X. Zeng, X. Li, and D. Zheng, “A Small-Area, Low-Power Delta-Sigma DAC Applied to a Power-Specific Chip,” J. Sensors, vol. 2021, pp. 1-8, May. 2021.
[22] S. Luo and D. Li, “A digital input Class-D audio amplifier with sixth-order PWM,” J. Semiconductors, vol. 34, no. 11, pp. 103-108, Nov. 2013.
[23] V. Colonna, M. Annovazzi, G. Boarin, G. Gandolfi, F. Stefani and A. Baschirotto, “A 0.22-mm2 7.25-mW per-channel audio stereo-DAC with 97-dB DR and 39-dB SNRout,” IEEE J. Solid-State Circuits, vol. 40, no. 7, pp. 1491-1498, Jul. 2005.
[24] C. Wei, J. Wu, R. Wei, M. He, “High-Fidelity and High-Efficiency Digital Class-D Audio Power Amplifier,” J. Electr. Comput. Eng., vol. 2021, pp. 1-10, Apr. 2021.
[25] S. Kim, N. Cho, S. -J. Song and H. -J. Yoo, “A 0.9 V 96 μW Fully Operational Digital Hearing Aid Chip,” IEEE J. Solid-State Circuits, vol. 42, no. 11, pp. 2432-2440, Nov. 2007.
[26] A. Mukhtar, H. Jamal and U. Farooq,“An area efficient interpolation filter for digital audio applications,” IEEE Trans. Consumer Electron., vol. 55, no. 2, pp. 768-772, May. 2009.
[27] M. Kang, H. Kim, J. Gu, W. Lim, J. Ham, H. Jung, and Y. Yang,“Low-Power and High-Efficiency Class-D Audio Amplifier Using Composite Interpolation Filter for Digital Modulators,” J. Semiconductor Technology and Science, vol. 14, no. 1, pp. 109-116, Feb. 2014.