由於物聯網時代的來臨，讓單次/多次編程唯讀記憶體元件的使用更為廣泛，其中傳統的機制分為三大類：(1) 熔絲崩潰(fuse breakdown) (2) 反熔絲崩潰(anti-fuse breakdown) (3) 電荷儲存(Charge-based)。本文所要解決的是單次編程記憶體進行編程時，編程電壓以及佈局面積過大的問題。本實驗室團隊提出了一個新的編程方式，亦即利用雪崩式崩潰作用於源極/汲極之PN接面，可有效的降低編程電壓，在電路佈局方面也利用共線設計，降低所需面積，提升此設計在唯讀記憶體元件上的競爭力。
因此，本文以14奈米鰭式電晶體來製作嵌入式單次編程記憶體。首先，我們將P型鰭式電晶體之閘極與基板端浮接，源極或汲極施加大偏壓，另一端接地，使得汲極或源極與基板之PN接面擁有非常大的電壓差。從能帶圖的概念可得知，當汲極/源極抬升時，將使得有少數電子可從價電帶下方穿隧至通道端，在穿隧過程中將會撞擊到路徑中的電子電洞對，產生離子碰撞使得電流上升，離子碰撞效應愈發劇烈會發生雪崩式崩潰，使得電流原本在0.1mA等級，急遽下降至0.1pA等級，以此觀念來設計單次編程記憶體。
同時，吾人也利用隨機電報雜訊(Random Telegraph Noise)技術，來探討裝置在編程模式下，缺陷的主要分佈情形，以此來說明此編程機制是發生在PN接面附近。在電路設計方面，使用了共線的概念，可大幅減少功耗以及佈局面積。因為共線之電路架構，在編程與讀取模式下之干擾測試也做了較多情況的探討。
本文設計的嵌入式單次編程記憶體，在編程上有較快的操作速度與較低的操作電壓，另外在防止編程擾動上也相當傑出，也能有效的改善因編程電壓導致的可靠度問題。除上述外，我們也探討了不同通道長度與編程電壓之間的關係，發現通道長度與編程電壓成正比，亦即當通道長度越小的情況下，編程電壓也會越低。在未來技術節點微縮的情況下，編程電壓也會隨之降低，能大幅降低功耗。而本研究的設計除具上述優點外，也具有優越的資料保存性與小面積等特性，在物聯網時代中，可以滿足嵌入式系統的儲存使用需求，是下一世代相當實用的單次編程記憶體。

In the history of the development of OTP memory, many existing structures of fuse breakdown devices used a narrow wire of metal or poly-silicide wire. On the other hand, anti-fuse breakdown devices formed an electrically conductive path permanently in the dielectric after a large external electric field applying on the gate. What this thesis is going to discuss is the problem of too large programming voltage and layout area for the design of one-time programming memory. Our team proposed a new programming method, using avalanche breakdown incurred at the source/drain PN junction, which can effectively reduce the programming voltage, and also used the common-line design in the circuit to reduce the required area and enhance the competitiveness of this design on read-only memory components.
Therefore, in this thesis, we used 14nm finFET to design embedded one-time programming memory. First, we keep the gate and substrate floating in a p-channel finFET, applying a large bias to the source or drain, and ground the other side, so that the PN junction between the drain or source to the substrate has a very large electrical potential. From the concept of the energy band diagram, it can be known that when the source or drain side is uplifted, a small number of electrons can tunnel from below the valence band to the channel. During the tunneling process, it will hit the electron-hole pair in the path, high-level current occurs when the impact ionization happens in the depletion region of channel. It further leads to the avalanche breakdown because of the higher reversed bias, which caused the current to drop to 0.1pA level originally at 0.1mA level, from which different two states can be used as the one-time programming memory.
Random Telegraph Noise technology has also been used to explore the main distribution of trap in the programming mode of the device, so as to explain that this programming mechanism occurs near the PN junction. In terms of circuit design, the concept of common line method is used. Bit lines and source lines of the same voltage are required for different cells, which can greatly reduce power consumption and layout area. Because of this circuit architecture, the disturbance test in the programming and reading modes have also been discussed more often.
Finally, based on this new scheme, we designed an embedded one-time programming memory, which has a larger on/off current ratio compared to that of reported results. In addition to the above, we also explored the relationship between the different channel lengths and the programming voltage, and found that the channel length is proportional to the programming voltage. The longer of the channel length becomes, the higher of the programming voltage will be. It means that long channel length can tolerate the avalanche breakdown, which can greatly reduce power consumption in the future. Finally, an embedded one-time programming memory has been demonstrated successfully on a 14nm FinFET platform to meet the requirements of security applications in IoT era.

[1.1] J. Raszka, M. Advani, V. Tiwari, L. Varisco, N. D. Hacobian, A. Mittal, M. Han, A. Shirdel, and A. Shubat, “Embedded Flash Memory for Security Applications in a 0.13 μm CMOS Logic Process,” in Proc. IEEE ISSCC. Dig. Tech. Papers, 2004, vol. 1, pp. 46–512.
[1.2] J. Rosenberg, “Embedded Flash on a CMOS Logic Process Enables Secure Hardware Encryption for Deep Submicron Designs,” in Proc. Non-Volatile Memory Technol. Symp., 2005, pp. 19–21.
[1.3] H. -K. Cha, I. Yun, J. Kim, B. -C. So, K. Chun, I. Nam, and K. Lee,“A 32-kB Standard CMOS Anti-fuse One-Time Programmable ROM Embedded in a 16-bit Microcontroller,” IEEE J. Solid-State Circuits, vol. 41, no. 9, pp. 2115–2124, 2006.
[1.4] J. Peng, G. Rosendale, M. Fliesler, D. Fong, J.Wang, C. Ng, Z. S. Liu, and H. Luan, “A Novel Embedded OTP NVM Using Standard Foundry CMOS Logic Technology,” in Proc. 21st IEEE NVSMW, 2006, pp. 24–26.
[1.5] V. Srinivasan, G. J. Serrano, J. Gray, and P. Hasler, “A Precision CMOS Amplifier Using Floating-Gate Transistors for Offset Cancellation,” IEEE J. Solid-State Circuits, vol. 42, no. 2, pp. 280–291, 2007.
[1.6] S. Babar, A. Stango, N. Prasad, J. Sen, and R. Prasad, “Proposed Embedded Security Framework for Internet of Things (IoT),” IEEE (Wireless VITAE), 2011,.
[1.7] C. Kothandaraman, S. K. Iyer, and S. S. Iyer, “Electrically Programmable Fuse (eFUSE) Using Electromigration in Silicides,” IEEE Electron Device Lett., vol. 23, no. 9, pp. 523–525, 2002.
[1.8] J. Safran, A. Leslie, G. Fredeman, C. Kothandaraman, A. Cestero, X. Chen, R. Rajeevakumar, D.-K. Kim, Y. Z. Li, D. Moy, N. Robson, T. Kirihata, and S. Iyer, “A Compact eFUSE Programmable Array Memory for SOI CMOS,” in VLSI Symp. Tech. Dig., 2007, pp. 72–73.
[1.9] G. Uhlmann, T. Aipperspach, K. Chandrasekharan, Y. Z. Li, C. Paone, B. Reed, N. Robson, J. Safran, D. Schmit, and S. Iyer, “A Commercial Field-Programmable Dense eFuse Array Memory with 99.999% Sense Yield for 45nm SOI CMOS,” IEEE, ISSCC Dig., 2008, pp. 406.
[2.1] H. Suto, S. Mori, M. Kanno, and N. Nagashima, “Programming Conditions for Silicided Poly-Si or Copper Electrically Programmable Fuses,” IEEE IRW, 2007 , pp. 84-89.
[2.2] M. -C. Hsieh, Y. -C. Lin, Y. -W. Chin, T .-S. Chang, Y. -C. King, and C. -J. Lin, “Characterization of Multilayer Metal Gate Fuse in 28-nm CMOS Logic Technology,” IEEE Electron Device Lett., vol. 34, no. 9, pp. 1088–1090, 2013.
[2.3] A. Hoefler, C. Henson, C. N. Li, and D. G. Lin, "Analysis of a Novel Electrically Programmable Active Fuse for Advanced CMOS SOI One-Time Programmable Memory Applications," 2006 European Solid-State Device Research Conference, Montreux, 2006, pp. 230-233.
[2.4] R. S.-J. Shen, M.-Y. Wu, H.-M. Chen, and C. C.-H. Lu, “A High-Density Logic CMOS Process Compatible Non-Volatile Memory for Sub-28nm Technolgoies,” IEEE, VLSI Tech Dig., pp. 34-35, 2014.
[2.5] SHEN, Rick Shih-Jye, et al, “A High-Density Logic CMOS Process Compatible Non-Volatile Memory for Sub-28nm Technologies,” IEEE VLSI Tech Dig., 2014.
[2.6] C. E. Huang, Y. J. Chen, H. C. Lai, Y. C. King, and C. J. Lin, "A Study of Self-Aligned Nitride Erasable OTP Cell by 45-nm CMOS Fully Compatible Process," in IEEE Transactions on Electron Devices, vol. 56, no. 6, pp. 1228-1234, June 2009.
[2.7] E. R. Hsieh, Z. H. Huang, S. S. Chung, J. C. Ke, C. W. Yang, C. T. Tsai, and T. R. Yew, "The Demonstration of Low-Cost and Logic Process Fully-Compatible OTP Memory on Advanced HKMG CMOS with a Newly Found Dielectric Fuse Breakdown," 2015 IEEE International Electron Devices Meeting (IEDM), Washington, DC, 2015, pp. 3.4.1-3.4.4.
[4.1] R. Bez, E. Camerlenghi, A. Modelli, and A. Visconti, “Introduction to Flash Memory,” in Proc. IEEE, vol. 91, no. 4, pp. 489–502, 2003.
[4.2] A. Silvagni, G. Fusillo, R. Ravasio, M. Picca, and S. Zanardi, “An Overview of Logic Architecture inside Flash Memory Devices,” in Proc. IEEE, vol. 91, no. 4, pp. 569–580, 2003.
[4.3] S. B. Herner, A. Bandyopadhyay, S. V. Dunton, V. Eckert, J. Gu, K. J. Hsia, S. Hu, C. Jahn, D. Kidwell, M. Konevecki, M. Mahajani, K. Park, C. Petti, S. R. Radigan, U. Raghuram, J. Vienna, and M. A. Vyvoda, “Vertical P-I-N Polysilicon Diode with Antifuse for Stackable Field-Programmable ROM,” IEEE Electron Device Lett., 2004, vol. 25, no. 5, pp. 271–273.
[4.4] S. Lai, “Current Status of the Phase Change Memory and Its Future,” in IEDM Tech. Dig., 2003, pp. 255–258.
[4.5] Y. -H. Tsai, H. -M. Chen, H. -Y. Chiu, H. -S. Shih, H. -C. Lai, Y. -C. King, and C. -J. Lin, “45 nm Gateless Anti-fuse Cell with CMOS Fully Compatible Process,” in IEDM Tech. Dig., 2007, pp. 95–98.
[4.6] M. Chen, C. -E. Huang, Y. -H. Tseng, Y. -C. King, and C. -J. Lin, “A New Antifuse Cell with Programmable Contact for Advance CMOS Logic Circuits,” IEEE Electron Device Lett., vol. 29, no. 5, pp. 522–524, 2008.
[4.7] J. He, W. T. Chan, C. Wang, H. Lou, R. Wang, L. Li, H. Liang, W. Wu, Y. Ye, Y. Ma, Q. Chen, X. He, and M. Chan, “A Compact CMOS Compatible Oxide Antifuse with Polysilicon Diode Driver,” IEEE Trans. Electron Devices, vol. 59, no. 9, pp. 2539–2541, 2012.
[4.8] S. H. Kulkarni, C. Zhanping, J. He, J. Lei, M. B. Pedersen, and K. Zhang, “A 4kb Metal-Fuse OTP-ROM Macro Featuring a 2V Programmable 1.37 μm2 1T1R Bit Cell in 32 nm High-K Metal-Gate CMOS,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 863–868, 2010.
[4.9] M. Shi, J. He, L. Zhang, C. Ma, X. Zhou, H. Lou, H. Zhuang, R. Wang, Y. Li, Y. Ma, W. Wu, W. Wang, and M. Chan, “Zero-Mask Contact Fuse for One-Time-Programmable Memory in Standard CMOS Processes,” IEEE Electron Device Lett., vol. 32, no. 7, pp. 955–957, 2011.
[4.10] R. Ranjan, T. Nigam, Y. Liu, A. Gondal, et al, “Reliability of 2T-core CMOS OTP non-volatile memory bitcells,” in 2017 IEEE International Reliability Physics Symposium (IRPS), 2017.
[4.11] C. C. Lin and Y.-H. Wu, “One-Time Programmable Memory Based on ZrTiOx Antifuse for Crossbar Memory Application Featuring High Speed Operation and Low Power Consumption,” IEEE Electron Device Lett., vol. 34, pp. 1518, 2013.
[5.1] Z. Chen, S. H. Kulkarni, V. E. Dorgan, S. M. Rajarshi, L. Jiang, and U. Bhattacharya, "A 0.9-μm² 1T1R Bit Cell in 14-nm High-Density Metal Fuse Technology for High-Volume Manufacturing and In-Field Programming," in IEEE Journal of Solid-State Circuits, vol. 52, no. 4, pp. 933-939, April 2017.
[5.2] S. H. Kulkarni, Z. Chen, B. Srinivasan, B. Pedersen, U. Bhattacharya, and K. Zhang, "Low-Voltage Metal-fuse Technology Featuring a 1.6V-Programmable 1T1R Bit Cell with an Integrated 1V Charge Pump in 22nm tri-gate process," 2015 Symposium on VLSI Technology (VLSI Technology), Kyoto, 2015, pp. C174-C175.