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研究生：	葉晏菱 Ye, Yan-Ling
論文名稱：	具有減少穩定時間技術的高速逐次逼近式類比數位轉換器 High-Speed SAR ADC with Settling Time Reduction Technique
指導教授：	郭建宏 Kuo, Chien-Hung
學位類別：	碩士 Master
系所名稱：	電機工程學系 Department of Electrical Engineering
論文出版年：	2020
畢業學年度：	108
語文別：	中文
論文頁數：	65
中文關鍵詞：	逐次逼近式類比數位轉換器、電容式數位類比轉換器、減少穩定時間技術、比較器
英文關鍵詞：	Successive Approximation Register Analog-to-Digital Converter, Capacitive DAC array, Capacitor settling time reduction technique, Comparator
DOI URL：	http://doi.org/10.6345/NTNU202000485
論文種類：	學術論文
相關次數：	點閱：189 下載：27
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隨著半導體製程技術不斷向前推進，智慧型裝置儼然成為時下最熱門的消費性電子產品，輕薄短小且高效能則成為電路設計的主流，需要透過類比數位轉換器來實現。在眾多架構裡，沒有繁冗的架構且需求的元件較少，再加上製程的提升，高效能的特點，在高取樣率的電路需求中被廣泛地使用，即是逐次逼近式類比數位轉換器最為合適。
　　本論文中，提出了減少電容切換的穩定時間技術來有效地提高整體電路的操作速度，相較於傳統的DAC架構，在相同的總電容量下，使用兩組DAC，讓每次切換減少了兩倍的時間。此外，N位元的電路使用N個比較器使得SAR ADC比較後不必透過暫存的方式而是直接回傳比較結果給DAC的開關進行切換，大幅地加速整體運作速度。在供應電源為1.2-V操作下，本研究採用TSMC 90nm 1P9M的製程，取樣頻率為400MHz，輸入訊號頻率為199.85MHz的模擬下，可達到的信號雜訊失真比為48.71dB，DNL和INL分別為+0.24/ -0.22及+0.22/ -0.5，總消耗功率為4.77mW，品質因數為53.5-fJ/conversion-step。

With the improvement of semiconductor technology, smart devices have turned into one of the most popular consumer electronics. The requirement for a smaller size with high performance has become the mainstream in circuit design. To reach that requirement, an analog-to-digital converter will be needed in analog design. Among all the structures, successive approximation register analog-to-digital converter (SAR ADC) is the simplest and requires less circuit components. Also, with the advance of manufacturing process, its high performance and high sampling rate make it widely used in the circuit. Therefore, SAR ADC will be our best choice.
　　In this thesis, a capacitor switching with settling time reduction (STR) technique is proposed to effectively enhance the operation speed of the overall circuit. Compared to the conventional DAC structure, with the same total capacitance, the two sets of DACs in the proposed structure are able to reduce the time by two in every switching. Besides, by using N comparators in an N-bit circuit, the SAR ADC does not need a temporary storage after comparison. Rather, the comparison result can directly be sent back to the DAC for switching and thus greatly accelerate the overall operation. Under 1.2V supply voltage, this work utilizes TSMC 90nm 1P9M manufacturing process. Under 400MHz sampling rate and with 199.85MHz input signal frequency, the simulation SNDR of the proposed ADC is 48.71dB. The DNL and INL are +0.24/-0.22 and +0.22/-0.5, respectively. The total power consumption is 4.77mW, and the FOM is 53.5fJ/conversion-step.

謝辭  i
中文摘要  iii
英文摘要  v
目錄  vii
表目錄  xi
圖目錄  xiii

第一章　　緒論  1
1　　研究動機與背景  1
2　　混合信號系統概述  2
3　　積體電路設計流程  2
4　　論文架構與研究方法  4

第二章　　類比數位轉換器基本原理  5
1　　前言  5
2　　基本原理  6
2.1　解析度  6
2.2　量化器  6
2.3　靜態參數  11
2.4　動態參數  15
2.5　品質因數  17
3　　逐次逼近式類比數位轉換器  18
3.1　二分搜尋演算法  19
3.2　SAR ADC運作流程  19

第三章　　SAR ADC基本電路元件  21
1　　前言  21
2　　取樣保持電路與開關元件  21
2.1　MOS開關  22
2.2　傳輸閘開關  24
2.3　靴帶式開關  25
3　　比較器  28
3.1　非理想效應  28
3.2　動態比較器  29
4　　真單相位時脈電路  32
5　　逐次逼近暫存器  33
6　　數位類比轉換器  34
6.1　電阻式數位類比轉換器  34
6.2　電流式數位類比轉換器  36
6.3　電容式數位類比轉換器  36

第四章　　減少穩定時間技術之SAR ADC  39
1　　前言  39
2　　電荷重新分佈原理  40
3　　減少穩定時間技術  41
4　　減少穩定時間技術之SAR ADC設計與模擬  45
5　　電路佈局與實現  50
6　　晶片量測環境  51
6.1　　輸入終端電路  52
6.2　　電壓調節電路  52
6.3　　濾波槽電路  53
7　　量測考量  53

第五章　　總結與未來展望  57
1　　總結  57
2　　未來展望  58

參考文獻  59
作者簡歷  63
學術成就  65
                                

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