在先進的半導體技術中，奈米片技術(Nanosheet, NS)應用於閘極環繞（Gate-all-around, GAA）電晶體和互補場效電晶體 (Complementary FET, CFET)，由於其優越的閘極控制能力和更高的密度，已成為最新的技術趨勢。然而，這項技術也面臨諸多挑戰，尤其是奈米片間距（Tsus）的空間限制及 CFET 對於低溫製程的限制，使得調變多階臨界電壓（VT）變得越來越困難。
研究從使用物理氣相沉積(Physical vapor deposition, PVD)電偶極層(Dipole layer)的金屬氧化物電容(MOSCAP)元件開始，逐步討論至原子層沉積(Atomic layer deposition, ALD)電偶極層元件。在PVD 電偶極層元件系列實驗，本實驗嘗試兩種材料Indium oxide (In2O3) 與 Aluminum oxide (Al2O3)，並分別製作電偶極層優先(Dipole-first)及電偶極層置後(Dipole-last) 元件，且製程溫度皆不超過500 °C，控制在低溫製程，具低熱預算的特性，本研究中可以看到In2O3 Dipole-first 元件在平整帶電壓位移 (Flat band voltage shift, VFB shift)的表現優異，最大的 VFB shift 達 -380 mV ，另外在以Al2O3作為電偶極層的元件也成功展示不同方向的VFB shift值達290 mV，實現多階的平整帶電壓調變。
綜上所述，多階臨界電壓之技術研究在先進的半導體技術中的發展前景廣闊，但需克服製程複雜性、熱預算和臨界電壓調整等多方面的挑戰，本論文透過研究此創新技術來推動臨界電壓調變技術的進一步發展。

In advanced semiconductor technology, nanosheet technology is applied in Gate-all-around (GAA) transistors and Complementary Field-Effect Transistors (CFET) due to its superior current control ability and higher density, making it the latest technological trend. However, this technology also faces numerous challenges, particularly the spatial limitations of nanosheet spacing (Tsus) and the constraints of CFET on low-temperature processes, which make multi-stage threshold voltage (VT) modulation increasingly difficult.
The research begins with PVD dipole layer devices and gradually discusses ALD dipole layer devices. In PVD dipole layer devices, we tried two materials: Indium oxide (In2O3) and Aluminum oxide (Al2O3), and fabricated both Dipole-first and Dipole-last devices, with process temperatures not exceeding 500 °C, showcasing the characteristic of low thermal budget. In this thesis, the In2O3 dipole-first devices demonstrated outstanding performance in flat band voltage shift (VFB shift), achieving a maximum VFB shift of -380 mV. Additionally, devices employing Al2O3 as the dipole layer successfully exhibited VFB shifts in a divergent direction, reaching values up to 290 mV, overall achieving multi-stage flat-band voltage modulation.
In summary, technical researches on multi-stage threshold voltage in advanced semiconductor technology have broad development prospects but must overcome challenges in process complexity, thermal budget, and threshold voltage adjustment. This study aims to promote further development through technological innovation.

[1] K. Y. Cheng, “Introduction. In: III–V Compound Semiconductors and Devices.”, in Springer Cham, 2020, pp.1-9.
[2] S. Barraud, B. Previtali, C. Vizioz, J.-M. Hartmann, J. Sturm, J. Lassarre, C. Perrot, Ph. Rodriguez, V. Loup, A. Magalhaes-Lucas, R. Kies, G. Romano, M. Cassé, N. Bernier, A. Jannaud, A. Grenier, F. Andrieu. ‘‘7-Levels-Stacked Nanosheet GAA Transistors for High Performance Computing,’’ in VLSI Technology Symp., 2020, TC1.2.
[3] Y. J. Mii, ‘‘Semiconductor innovations, from device to system,’’ in VLSI Technology Symp., 2022, pp. 276-281.
[4] P. Schuddinck, F. M. Bufler, Y. Xiang, A. Farokhnejad, G. Mirabelli, A. Vandooren, B. Chehab, A. Gupta, C. Roda Neve, G. Hellings and J. Ryckaert.,‘‘PPAC of sheet-based CFET configurations for 4 track design with 16nm metal pitch,’’ in VLSI Technology Symp., 2022, pp. 365-366.
[5] Z. Q. Liu, W. K. Chim, S. Y. Chiam, J. S. Pan and C. M. Ng. ‘‘An interface dipole predictive model for high-k dielectric/semiconductor heterostructures using the concept of the dipole neutrality point,’’ Journal of Materials Chemistry., 2012, 22, 17887–17892.
[6] K. Kita, A. Toriumi, ‘‘Origin of electric dipoles formed at high-k/SiO2 interface,’’ Applied Physics Letters, 2009, vol. 94, iss. 13, 132902.
[7] A. Toriumi, T. Nabatame, ‘‘Anomalous VFB Shift in High-k Gate Stacks-Is its Origin at the Top or Bottom Interface?- ,’’ ECS Transactions, vol. 25, no. 6, pp. 3-16, 2009.
[8] H. Arimura, L.-Å. Ragnarsson, Y. Oniki, J. Franco, A. Vandooren, S. Brus, A. Leonhardt , P. Sippola1 , T. Ivanova1 , G. Alessio Verni , R.-J. Chang , Q. Xie , M. Givens , J. Mitard, S. Biesemans, E. Dentoni Litta, and N. Horiguchi. ‘‘Dipole-first gate stack as a scalable and thermal budget flexible multi-Vt solution for nanosheet/CFET devices,’’ in IEDM Tech. Dig., 2021, pp. 290-293.
[9] J. Yao, Y. Wei, S. Yang, H. Yang, G. Xu, Y. Zhang, L. Cao, X. Zhang, Q. Liu, Z. Wu, H. Yin, Q. Zhang, J. Li and J. Luo., ‘‘Record 7 (N)+ 7 (P) Multiple VT s Demonstration on GAA Si Nanosheet n/pFETs using WFM-Less Direct Interfacial La/Al-Dipole Technique,’’ in IEDM Tec. Dig., 2022, pp. 811-814.
[10] H. Arimura, H. Mertens, J. Franco, L. Lukose, W. Maqsood, S. Brus, T. Chiarella, A. Impagnatiello, S. Homkar, V. K. Mootheri, C. Yin, G. A. Verni, M. Givens, L. P. B. Lima, S. Biesemans and N. Horiguchi, “Vt Fine-Tuning in Multi-Vt Gate-All-Around Nanosheet nFETsusing Rare-Earth Oxide-based Dipole-First Gate Stack Compatible with CFET Integration”in VLSI Technology Symp, 2024, pp 11.1.
[11] S. H. Su, H. J. Kong, C. L. Tseng and G. Y. Chen.,‘‘Wet etching mechanism and crystallization of indium–tin oxide layer for application in light-emitting diodes,’’ Japanese Journal of Applied Physics., 2017, vol. 57, 01AE05.
[12] R. Bao, H. Zhou, M. Wang, D. Guo, BS. Haran, V. Narayanan, R. Divakaruni, “Extendable and manufacturable volume-less multi-Vt solution for 7nm technology node and beyond.”, IEDM, 2018, pp. 28.5.1-28.5.4.
[13] R. Bao, K. Watanabe, J. Zhang, J. Guo, H. Zhou, A. Gaul, M. Sankarapandian, J. Li, A. R. Hubbard, R. Vega, S. Pancharatnam, P. Jamison, M. Wang, N. Loubet, V. Basker, D. Dechene, D. Guo, B. Haran, H. Bu, M. Khare, “Multiple-Vt Solutions in Nanosheet Technology for High Performance and Low Power Applications”, IEDM, 2019, pp. 11.2.1-11.2.4.
[14] H. Arimura, H. Mertens, J. Franco, L. Lukose, W. Maqsood, S. Brus, T. Chiarella, A. Impagnatiello, S. Homkar , V. K. Mootheri , C. Yin , G. A. Verni , M. Givens , L. P. B. Lima, S. Biesemans and N. Horiguchi, “Vt Fine-Tuning in Multi-Vt Gate-All-Around Nanosheet nFETs using Rare-Earth Oxide-based Dipole-First Gate Stack Compatible with CFET Integration, ” in VLSI Symp., 2024, 11.1.