目前的監視系統大都使用攝影機來做為監視的工具，然而此類的攝影機是將影像擷取後送至主控室，由監視人員透過監視人員透過螢幕來做監視，如此對監視人員的精神實在是一大負荷。較先進的監視系統會先將攝影機所擷取的影像透過電腦系統加以分析，以達到自動監視的目的，然而此種監視系統需要大量的電腦設備。

本論文的目的是想發展一種聰明型攝影機，希望此類聰明型攝影機能夠自己去分析、偵測可疑的目標物，最後再將此目標物的特徵及位置傳回電腦端。如此監視系統即不用監視人員緊盯著螢幕監視，也無須龐大的電腦設備即可達到自動監視的目的。

本論文中我們以硬體設計了一個CMOS攝影機的控制界面電路，可以直接讀取攝影機所拍攝到的影像。另外也設計了一個可程式規劃(programmable)的型態運算(morphological operation)電路，可以對所擷取的影像做處理。為了驗證所提出的架構可以即時的處理，我們也設計了一個VGA顯示器控制界面，可將運算後的結果以灰階影像直接顯示在螢幕上。整個系統的發展是以SOPC (System On Programmable Chip)為平台，利用硬體描述語言(Hardware Description Language)所發展而成。

Presently, most cameras are used to supervise as a monitor system. As the camera captures the images, it transmits the images to spotters as soon as possible. However, it is neither smart nor efficient to supervise the images by supervisors. In order to supervise automatically, an advanced monitor system can analyze the obtained images through the monitor system itself. At the same time, a large number of computer devices are required in such a monitor system.
The main idea for this thesis is to develop a smart camera. The camera is capable of detecting the wanted objects and analyzing. Then transmit the related information of the objects like features and position to the receiver without delay. Without staring the monitor screen all the time by the supervisors, the smart camera achieves supervising automatically. Obviously, the cost is reduced due to the less devices.
In this thesis, we design a camera controller of the CMOS camera by hardware. The controller reads the images directly. Besides, we add a programmable morphological operation to process images. For verifying the real-time processing system, the Lancelot VGA controller is improved to display the result in grayscale image through the monitor screen. The platform is based on SOPC (System On Programmable Chip) with using hardware description language to develop the system.

[1] A. Ben Atitallah, P. Kadionik, F. Ghozzi, P.Nouel, N.Masmoudi, Ph.Marchegay, “Hardware Platform Design for Real-Time Video Applications,” IEEE ICM Proceedings, 2004.
[2] J. Velten, A. Kummert, “FPGA-based Implementation of variable sized structuring elements for 2D binary morphological operations,” IEEE Electronic Design, Test and Applications, 2002.
[3] Scott Hemmert, Brad Hutchings and Anshul Malvi, “An Application-Specific Compiler for High-Speed Binary Image Morphology,” IEEE Field-Programmable Custom Computing Machines, 2001.
[4] Alexey Lukin, Denis Kubasov, “An improved Demosaicing Algorithm,” Graphicon’2004 conference proceedings.
[5] Fei Sun, S. Ravi, A. Raghunathan and N.K. Jha, “Custom-Instruction Synthesis for Extensible-Processor Platforms,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, pp.216-228, Feb. 2004.
[6] B. Dalay, “Accelerating System Performance using SOPC Builder,” SOC International Symposium, pp.3-5, Nov. 2003.
[7] M. Finc and A. Zemva, “Rapid HW/SW Co-design of Softcore Processor Systems,” IEEE Region 8 Computer as a Tool, vol.1, pp.104-108, Sept. 2003.
[8] Takashi Komuro, Idaku Ishii, Masatoshi Ishikawa, and Atsushi Yoshida, “A Digital Vision Chip Specialized for High-Speed Target Tracking,” Electron Devices, IEEE Transactions on Volume 50, issue 1, Jan. 2003 Page(s):919-199.
[9] Altera Corporation. http://www.altera.com, 2005.
[10] Altera Nios Development Kit 3.10 Documentations, 2004.
[11] Tasc Corporation. http://www.tascorp.com.tw
[12] TAS5130D1B/TAS5030D1B VGA CMOS Image Sensor Technical Specification. Initial Version 0.05, 2004.
[13] http://www.fpga.nl
[14] Michael D. Ciletti . 2003. Advanced Digital Design with the VERILOG HDL.
[15] 蕭如宣，SOPC系統設計，儒林，2003.
[16] 鄭信源，VHDL數位電路設計(基礎篇)，儒林，2003.
[17] 鄭信源，VHDL數位電路設計(進階篇)，儒林，2003.
[18] 鄭信源，verilog 硬體描述語言數位電路設計實務，全華，2002.
[19] 盧毅，VHDL與數位電路設計，文魁資訊，2000.
[20] 洪錦魁，Turbo C 入門與應用徹底剖析，文魁資訊，1998，
[21] 古頤榛，VISUAL C++ 6 教學範本，碁峰資訊，2000.
[22] 李宜達，動態模擬與繪圖:使用MATLAB/SIMULINK，全華，1998.