研究生: |
廖俊宇 Liao, Chun-Yu |
---|---|
論文名稱: |
鐵電氧化鉿鋯之記憶體及鰭式電晶體 Ferroelectric HfZrO2 for FeRAM and FinFET |
指導教授: |
李敏鴻
Lee, Min-Hung |
學位類別: |
碩士 Master |
系所名稱: |
光電工程研究所 Graduate Institute of Electro-Optical Engineering |
論文出版年: | 2019 |
畢業學年度: | 107 |
語文別: | 中文 |
論文頁數: | 65 |
中文關鍵詞: | 鐵電記憶體 、氧化鉿鋯 、負電容電晶體 、鰭式電晶體 |
英文關鍵詞: | Fe-Memory, HfZrOx, NC-FETs, FinFET |
DOI URL: | http://doi.org/10.6345/THE.NTNU.EPST.002.2019.E08 |
論文種類: | 學術論文 |
相關次數: | 點閱:271 下載:0 |
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在半導體的領域中,電晶體在設計上追求精小,然而對效能的期望卻越來越高。因此,此領域的專家不斷地找尋新穎材料,嘗試加入在電晶體的製作中,希望能藉此突破現今所面臨的瓶頸。鐵電材料在近年來相當受到研究人員的注目,其材料擁有的雙穩態能被廣泛應用於記憶體的操作上。此外,鐵電材料中出現的負電容效應,有著電壓放大的效果,能有效打破次臨界擺幅(subthreshold swing, SS)的物理極限,以降低操作電壓VDD。
本篇論文研究將使用鐵電材料-氧化鉿鋯(HfZrO2, HZO)作為絕緣層,在MFM(Metal-Ferroelectric-Metal)結構中替換不同的上電極金屬,探討遲滯曲線特性的改變。而在記憶體追求簡單的電路設計概念下,利用HZO鐵電電晶體來做出1T記憶體。最後在鰭式電晶體的製程技術下,搭載鐵電薄膜來突破次臨界擺幅的極限,同時達到尺寸微縮及效能提升的結果。
In the semiconductor field, transistors are required to be extremely small; however, the functions are expected to be better and better. Therefore, experts in this field are always looking to find novel materials to apply in transistors to surmount the bottleneck. Ferroelectric materials get the researcher’s attention in recent years, because these materials have steady bipolar state in hysteresis loop, they can be used in memory function wildly. In addition, ferroelectric materials occur negative capacitance which has voltage amplification to challenge the subthreshold swing (SS) with physical limit, and is helpful to decrease the operation voltage VDD.
In this research, it is going to be about the use of ferroelectric materials, HfZrO2 (HZO), to be the insulator layer. The characteristic of hysteresis loop is discussed by changing different top electrode metal in MFM (Metal-Ferroelectric-Metal) structure. And memory circuit is under the concept of simple design, using HZO ferroelectric transistor to make 1T memory. The last, transistors carry up ferroelectric film to break through the physical limit of subthreshold swing with FinFET fabrication skill to achieve miniature size and increase performance.
[1] T. Boescke, J. Heitmann, U. Schroder, “Integrated circuit with dielectric layer, ” US 7,709,359 B2, 2010 (Filing date 2007-09-05).
[2] S. Müller, H. Mulaosmanovic, S. Slesazeck, J. Müller, and T. Mikolajick, “CMOS Compatible Ferroelectric Devices for Beyond 1X nm Technology Nodes, ” in SSDM, 2017, pp. 539-540.
[3] T. S. Bösckea, J. Müllerb, D. Bräuhausc, U. Schröderd, and U. Böttgerc, “Ferroelectricity in Hafnium Oxide: CMOS compatible Ferroelectric Field Effect Transistors, ” in International Electron Device Meeting (IEDM), pp. 547-550, 2011.
[4] P. Polakowski, S. Riedel, W. Weinreich, M. Rudolf, J. Sundqvist, K. Seidel, and J. Müller, “Ferroelectric deep trench capacitors based on Al:HfO2 for 3D nonvolatile memory Applications, ” in IMW, 2014.
[5] C. H. Cheng and A. Chin, “Low-Leakage-Current DRAM-Like Memory Using a One-Transistor Ferroelectric MOSFET With a Hf-Based Gate Dielectric, ” IEEE Electron Device Letter, vol. 35, pp. 138-140, 2014.
[6] C. H. Cheng and A. Chin, “Low-Voltage Steep Turn-On pMOSFET Using Ferroelectric High-κ Gate Dielectric, ” IEEE Electron Device Letter, vol. 35, pp. 274-276, 2014.
[7] M. H. Park, H. J. Kim, Y. J. Kim, T. Moon,K. D. Kim, and C. S. Hwangn, “Toward a multifunctional monolithic device based on pyroelectricity and the electrocaloric effect of thin antiferroelectric HfxZr1-xO2 films, ” Nano Energy, vol. 12, pp. 131-140, 2015.
[8] Y. C. Chiu, C. H. Cheng, C. Y. Chang, M. H. Lee, H. H. Hsuand, and S. S. Yen, “Low Power 1T DRAM/NVM Versatile Memory Featuring Steep Sub-60-mV/decade Operation, Fast 20-ns Speed, and Robust 85oC-Extrapolated 1016 Endurance, ” in VLSI Technology Symp., pp. 184-185, 2015.
[9] S. Fujii, Y. Kamimuta, T. Ino, Y. Nakasaki, R. Takaishi, and M. Saitoh, “First demonstration and performance improvement of ferroelectric HfO2-based resistive switch with low operation current and intrinsic diode property, ” in VLSI Technology Symp., pp. 978-979, 2016.
[10] H. Mulaosmanovic, J. Ocker, S. Müller, M. Noack, J. Müller, P. Polakowski, T. Mikolajick, and S. Slesazeck, “Novel ferroelectric FET based synapse for neuromorphic systems, ” in VLSI Technology Symp., pp. 176-177, 2017.
[11] R. Eskandari, X. Zhang, and L. M. Malkinski, “Polarization-dependent photovoltaic effect in ferroelectric-semiconductor system, ” Applied Physics Letters, vol. 110, 121105, 2017.
[12] M. Dragoman, M. Aldrigo, M. Modreanu, and D. Dragoman, “Extraordinary tunability of high-frequency devices using Hf0.3Zr0.7O2 ferroelectric at very low applied voltages, ” Applied Physics Letters, vol. 110, p. 103104, 2017.
[13] J. V. Houdt, “Memory Technology for the Terabit Era: from 2D to 3D, ” in VLSI Technology Symp., pp. 978-979, 2017.
[14] S. W. Smith, A. R. Kitahara, M. A. Rodriguez, M. D. Henry, and M. T. Brumbach, and J. F. Ihlefeld, “Pyroelectric response in crystalline hafnium zirconium oxide (Hf1-xZrxO2) thin films, ” Applied Physics Letters, vol. 110, 072901, 2017.
[15] F. Huang, Y. Wang, X. Liang, J. Qin, Y. Zhang, X. Yuan, Z. Wang, B. Peng,L. Deng, and Q. Liu, “HfO2-Based Highly Stable Radiation-Immune Ferroelectric Memory, ” IEEE Electron Device Letter, vol. 38, pp. 330-333, 2017.
[16] A. Chen, “Nanoelectronic Device Research for beyond - CMOS Technologies, ” in “Emerging Technologies for the post 14nm Node Area, ” in IEEE IEDM short course, Dec. 8, 2012.
[17] I. Chilibon, and J. Marat-Mendes, “Ferroelectric ceramics by sol-gel methods and applications: a review,” Journal of Sol-Gel Science and Technology, pp. 571-611, 2012.
[18] K. Ni, M. Jerry, J. A. Smith, and S. Datta, “A Circuit Compatible Accurate Compact Model for Ferroelectric-FETs,” in VLSI Technology Symp., 2018, pp. 131-132.
[19] International Technology Roadmap for Semiconductors (ITRS) Roadmap, 2009.
[20] S. Salahuddin, and S. Datta, “Can the subthreshold swing in a classical FET be lowered below 60 mV/decade,” in International Electron Device Meeting (IEDM), pp. 693-696, 2008.
[21] T. P. Ma and J.-P. Han, “Why is nonvolatile ferroelectric memory field-effect transistor still elusive?, ” IEEE Electron Device Letter, vol. 23, no. 7, pp. 386-388, Jul. 2002, DOI: 10.1109/LED.2002.1015207.
[22] R. R. Mehta, B. D. Silverman, amnd J. T. Jacobs, “Depolarization fields in thin ferroelectric films,” Journal of Applied Physics, vol. 44, no. 8, pp. 3379-3385, 1973.
[23] T. Shiraishi, K. Katayama, T. Yokouchi, T. Shimizu, T. Oikawa, O. Sakata, H. Uchida, Y. Imai, T. Kiguchi, T. J. Konno, and H. Funakubo, “Effect of the film thickness on the crystal structure and ferroelectric properties of (Hf0.5Zr0.5)O2 thin films deposited on various substrates,” Materials Science in Semiconductor Processing, pp. 239-245, 2017.
[24] Premier II Ferroelectric Test System Brochure
[25] M. H. Park, H. J. Kim, Y. J. Kim, T. Moon, and C. S. Hwang, “ The effects of crystallographic orientation and strain of thin Hf0.5Zr0.5O2 film on its ferroelectricity,” Applied Physics Letters, vol. 104, 2901, 2014.
[26] S. J. Kim, J. Mohan, H. S. Kim, J. Lee, C. D. Young, L. Colombo, S. R. Summerfelt, T. San, and J. Kim, “ Low-voltage operation and high endurance of 5-nm ferroelectric Hf0.5Zr0.5O2 capacitors,” Applied Physics Letters, vol. 113, 182903, 2018.
[27] 李明道, “各式記憶體簡介,” 國家奈米元件實驗室奈米通訊, vol. 22, no.4, pp. 2-6, 2015.
[28] 李明道, “新式非揮發性記憶體之發展與挑戰,” 國家奈米元件實驗室奈米通訊, vol. 21, no. 3, pp. 9-14, 2014.
[29] B1500A Semiconductor Device Analyzer user’s manual
[30] B1525A (B1500A-A25, B1500AU-025) High Voltage Semiconductor Pulse Generator Unit
[31] Agilent B1530A Waveform Generator/Fast Measurement Unit
[32] K. Chatterjee, S. Kim, G. Karbasian, A. J. Tan, A. K. Yadav, A. I. Khan, C. Hu, and S. Salahuddin, “Self-Aligned, Gate Last, FDSOI, Ferroelectric Gate Memory Device With 5.5-nm Hf0.8Zr0.2O2, High Endurance and Breakdown Recovery, ” IEEE Electron Device Letter, vol. 38, no. 10, pp.1379-1382, 2017, DOI: 10.1109/LED.2017.2748992.
[33] Y.-C. Chiu, C.-H. Cheng, C.-Y. Chang, M.-H. Lee, H.-H. Hsu and S.-S. Yen, “Low Power 1T DRAM/NVM Versatile Memory Featuring Steep Sub-60-mV/decade Operation, Fast 20-ns Speed, and Robust 85oC-Extrapolated 1016 Endurance, ” in VLSI Technology Symp., 2015, pp. T184-T185, DOI: 10.1109/VLSIT.2015.7223671.
[34] H. Mulaosmanovic, S. Slesazeck, J. Ocker, M. Pesic, S. Müller, S. Flachowsky, J. Müller, P. Polakowski, J. Paul, S. Jansen, S. Kolodinski, C. Richter, S. Piontek, T. Schenk, A. Kersch, C. Künneth, R. van Bentum, U. Schröder,and T. Mikolajick, “Evidence of single domain switching in Hafnium Oxide based FeFETs: enabler for multi-level FeFET memory cells, ” in International Electron Device Meeting (IEDM), 2015, pp. 688-690, DOI: 10.1109/IEDM.2015.7409777.
[35] H. Mulaosmanovic, J. Ocker, S. Müller, U. Schroeder, J. Müller, P.Polakowski, S. Flachowsky, R. van Bentum, T. Mikolajick, and S.Slesazeck, “Switching Kinetics in Nanoscale Hafnium Oxide Based Ferroelectric Field-Effect Transistors, ” ACS Appl. Mater. Interfaces, vol. 9, no. 4, pp. 3792-3798, 2017, DOI: 10.1021/acsami.6b13866.
[36] M. H. Lee, Y.-T. Wei, C. Liu, J.-J. Huang, M. Tang, Y.-L. Chueh, K.-Y. Chu, M.-J. Chen, H.-Y. Lee, Y.-S. Chen, L.-H. Lee, and M.-J. Tsai, “Ferroelectricity of HfZrO2 in Energy Landscape with Surface Potential Gain for Low-Power Steep-Slope Transistors, ” IEEE J. of the Electron Device Society, Vol. 3, No. 4, pp. 377-381, 2015, DOI: 10.1109/JEDS.2015.2435492.
[37] M. H. Lee, Y.-T. Wei, K. Y. Chu, J. J. Huang, C. W. Chen, C. C. Cheng, M. J. Chen, H. Y. Lee, Y. S. Chen, L. H. Lee, and M. J. Tsai, “Steep Slope and Near Non-Hysteresis of FETs With Antiferroelectric-Like HfZrO for Low-Power Electronics, ” IEEE Electron Device Letter, Vol. 36, No. 4, pp. 294-296, 2015, DOI: 10.1109/LED.2015.2402517.
[38] C. Hu, “ FinFET 3D Transistors and the Concept Behind it,” 2011.
[39] M. A. Karim, Sriramkumar Venugopalan, Yogesh Singh Chauhanm Darse Lu, Ali Niknejad, and Chenming Hu, “Drain Induced Barrier Lowering (DIBL) Effect on the Intrinsic Capacitances of Nano-Scale MOSFETs,” NSTI-Nanotech, pp. 814-817, 2011.
[40] S. Salahuddin, and S. Datta, “ Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices,” Nano Letters, vol. 8, no. 2, pp. 405-410, 2008.
[41] K.-S. Li, P.-G. Chen, T.-Y. Lai, C.-H. Lin, C.-C. Cheng, C.-C. Chen, Y.-J. Wei, Y.-F. Hou, M.-H. Liao, M.-H. Lee, M.-C. Chen, J.-M. Sheih, W.-K. Yeh, F.-L. Yang, S. Salahuddin, C. Hu, “ Sub-60mV-Swing Negarive-Capacitance FinFET without Hysteresis,” in International Electron Device Meeting (IEDM), pp. 620-623, 2015.
[42] Z. Krivokapic, U. Rana, R. Galatage, A. Razavieh, A. Aziz1, J.Liu, J.Shi, H.J. Kim, R. Sporer, C. Serrao, A.Busquet, P. Polakowski, J. Müller, W. Kleemeier, A. Jacob, D. Brown, A. Knorr, R. Carter, and S. Banna, “14nm Ferroelectric FinFET Technology with Steep Subthreshold Slope for Ultra Low Power Applications,” in International Electron Devices Meeting (IEDM), pp. 357-360, 2017.
[43] W. Chung, M. Si, and P. D. Ye, “Hysteresis-free Negative Capacitance Germanium CMOS FinFETs with Bi-directional Sub-60 mV/dec,” in International Electron Device Meeting (IEDM), pp. 365-368, 2017.
[44] H. Zhou, D. Kwon, A. B. Sachid, Y. Liao, K. Chatterjee, A. J. Tan, A. K. Yadav, C. Hu, and S. Salahuddin, “Negative Capacitance, n-Channel, Si FinFETs: Bi-directional Sub-60 mV/dec, Negative DIBL, Negative Differential Resistance and Improved Short Channel Effect,” in Symp. on VLSI Technology and Circuits, pp. 53-54, 2018.
[45] P. Sharma, K. Tapily, A. K. Saha, J. Zhang, A. Shaughnessy, A. Aziz, G.L. Snider, S. Gupta, R. D. Clark, S. Datta, “Impact of Total and Partial Dipole Switching on the Switching Slope of Gate-Last Negative Capacitance FETs with Ferroelectric Hafnium Zirconium Oxide Gate Stack,” in VLSI Technology Symp, pp. T154-T155, 2017.