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研究生: 謝忠政
Chung-Cheng Hsieh
論文名稱: 用FPGA實現之AES在音訊上的應用
A Dedicated AES System Application in Audio Signals Using FPGA
指導教授: 何宏發
Ho, Hong-Fa
黃奇武
Huang, Chi-Wu
學位類別: 碩士
Master
系所名稱: 電機工程學系
Department of Electrical Engineering
論文出版年: 2010
畢業學年度: 98
語文別: 中文
論文頁數: 83
中文關鍵詞: 高等加密標準現場可程式化閘陣列音訊即時
英文關鍵詞: AES, FPGA, Embedded System, Audio, Real time
論文種類: 學術論文
相關次數: 點閱:185下載:16
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  • 現今通訊系統之發達,使得人與人之間的溝通可以透過即時的通訊裝置如電話、手機乃至於電腦上之即時串流如會議系統、Skype…等,即可達到無時差的即時溝通,使得不論一般生活上的溝通乃至於商業活動、軍事通訊、政府機關等的溝通更加方便。然而方便的即時溝通環境和設備,但如果是必須保密的祕密通訊如商業、軍事或政府重大的機密決策等,通訊的安全就是首要的任務。
    本文主要在於實現更安全的音訊加密方式,實現方式為在周邊的硬體界面上設計了類比轉數位的轉換電路,可將由外界輸入之類比音訊轉換為數位音源,此轉換後的數位資料將是加密的基礎。之後在遠端的周邊上設計一數位轉類比的硬體電路,此可將加密過後或解密後的音訊由後端的喇叭輸出而聽到加密或解密的聲音變化。
    而主要實現音訊間的加∕解密系統,將採用進階加密標準(Advanced Encryption Standard,AES)演算法,並以其128位元的架構來實現,其中包括直接連線的移列轉換(ShiftRow)、並利用晶片內建的Block RAM來放置整合資料,完成位元組替換(SubByte)與混行運算(MixColumn)的動作以及存放金鑰擴展(KeyExpansion),來節省電路面積。

    For the communication system development rapidly nowadays, people communicate each other by immediate communication devices such as telephone, mobile and computer system which is the streaming system or the Skype software etc. These devices and software systems may accomplish the goal of immediate communication without time lag. It means that they provide convenience not only daily life but also business activities, military communication and government business. The first important mission is secure communication if they are involved in the secure decision levels in the business, military and government systems.

    The main goal of this report achieves a model of a secure immediate voice communication. The approach of achievement is by the design of analog to digital (A/D) converters in the hardware interface of peripherals. It converts analog voice signals of outside to digital voice signals. It is the basic information of encryption by the transformation from signals to digital data. Moreover, we may design a digital to analog (D/A) converters of hardware in the backend of peripherals and people can hear the variation of voices which are in the process of encryption and decryption by the end output of speakers.

    It uses the Advanced Encryption Standard (AES) Algorithm which is base on the architecture of 128 bits to archive the immediate voice encryption and decryption system. The system includes the direct connection of link ShiftRow, the Block RAM which is built in chipset and put all integrated information data, the execution of the SubByte, the MixColumn and the storage of the Key Expansion to reduce the space of circuit.

    摘  要 i ABSTRACT ii 誌  謝 iv 目  錄 v 表 目 錄 viii 圖 目 錄 ix 第一章 緒論 1 1.1 研究背景 1 1.2 研究動機 3 1.3 研究目的 4 1.4 研究步驟 5 第二章 AES演算法、音訊的處理及文獻探討 7 2.1 高等加密標準演算法介紹 7 2.1.1 演算法流程 7 2.1.2 位元組替換與反位元組替換 9 2.1.3 移列轉換與反移列轉換 11 2.1.4 混行運算與反混行運算 13 2.1.5 回合金鑰加法運算 15 2.1.6 金鑰的擴充 15 2.2 音訊的數位處理 18 2.2.1 聲音的形成 18 2.2.2 聲音的數位化 19 2.2.2.1 音訊類比至數位的轉換 19 2.2.2.2 音訊數位至類比的轉換 21 2.3 文獻探討 22 2.3.1 AES相關文獻 22 2.3.1.1 Ricardo Chaves[6]架構 22 2.3.1.2 Pawel Chodowiec[10]架構 24 2.3.1.3 Brokalakis[18]設計架構 26 2.3.2 音訊加解密相關文獻 27 2.3.2.1 保密影音通訊系統之設計與實現[20] 27 2.3.2.2 MP3編碼與AES演算法硬體實現[21] 28 2.3.2.3 網路即時通訊語音安全設計[22] 29 第三章 系統硬體架構與各單元設計 31 3.1 輔助儀器 31 3.2.1 函數產生器(Function Generator) 31 3.2.2 邏輯分析儀(Logic Analyzer) 32 3.2.3 示波器(Oscilloscope) 33 3.2.4 直流電源供應器(DC Power Supply) 33 3.2 音訊加/解密系統及其外部硬體電路 34 3.2.1 音訊「加密」系統周邊硬體電路解說 34 3.2.1.1 音訊輸入端放大電路及數位化轉換 36 3.2.1.2 音訊輸出端類比轉換及放大電路 38 2.3.1.3 音訊類比、數位間轉換之電路測試 38 3.2.2 音訊「解密」系統周邊硬體電路解說 39 3.3 音訊加密/解密引擎硬體架構 41 3.3.1 音訊加密引擎輸入/出界面硬體架構 41 3.3.1.1 音訊加密引擎輸入界面硬體架構 42 3.3.1.2 音訊加密引擎輸出界面硬體架構 44 3.3.2 音訊解密引擎輸入/出界面硬體架構 46 3.3.3 音訊加/解密引擎AES演算法硬體架構 50 3.3.3.1 音訊加/解密引擎AES Shift Row硬體架構 51 3.3.3.2 音訊加/解密引擎SubBytes、MixColumn硬體架構 52 3.3.3.3 音訊加/解密引擎回合金鑰的產生 55 3.3.3.4 加/解密引擎模擬與測試 55 3.3.4 音訊加/解密引擎其他控制界面 58 3.3.4.1 AES時脈啟動/停止電路 58 3.3.4.2 標示128 bits加/解密資料方塊之首筆資料 59 第四章 實驗成果分析 61 4.1 128位元AES電路效能比較 61 4.2 驗證平台規劃與加/解密引擎之實施 62 4.2.1 加密引擎硬體之實施 63 4.2.2 解密引擎硬體之實施 64 4.3 建構一完整之音訊加/解密系統 66 4.4 音訊加/解密系統之實驗成果 69 4.4.1 音訊加密後波型量測 69 4.4.2 音訊解密後波型量測 71 第五章 結論與未來展望 73 參考文獻 75 附 錄 一 78 附 錄 二 79 自  傳 80 學術成就 83

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