近幾年來，隨著無線通訊的快速發展，對於無線網路所要求的吞吐量也越來越高，且由於較低頻的2.4 GHz頻帶使用過於壅塞，導致電路設計上朝向同樣免授權免付費的5 GHz U-NII(Unlicensed National Information Infrastructure)頻帶發展，此外，對於無線收發器來說，功率放大器扮演著舉足輕重的角色，以往，為達高輸出功率與高效率，設計上會以砷化鎵(GaAs)製程為主，然而，互補式金氧半導體(CMOS)製程有著低成本及系統晶片整合的優點，故以5 GHz U-NII頻帶為重心的互補式金氧半導體功率放大器已成為現在的新趨勢，因此本論文將從電路設計的角度切入，設計及實現三個使用不同功率合成技術的5.2 GHz互補式金氧半導體功率放大器。
第一個電路為直接並聯功率合成技術之5~5.8 GHz功率放大器，將兩組功率元件直接並聯，藉此提高輸出功率，晶片佈局面積為0.875×0.705 mm2，在5.2 GHz時之量測增益(S21)為12.3 dB，並達到23.1 dBm的飽和輸出功率(Psat)，18.6 dBm的1dB增益壓縮輸出功率(OP1dB)及19.8%的最高功率輔助效率(PAE)，寬頻功率匹配架構的使用，使得功率放大器從5~5.8 GHz的飽和輸出功率為22.6±0.5 dBm。
第二個電路為兩路變壓器功率合成技術之5.2 GHz功率放大器，為了達到高功率輸出，利用變壓器實現功率合成，晶片佈局面積為1.2×0.6 mm2，量測增益(S21)為15.14 dB，飽和輸出功率(Psat)為25.81 dBm，1dB增益壓縮輸出功率(OP1dB)為21.42 dBm，最高功率輔助效率(PAE)為27.58%。
第三個電路為串聯結合變壓器功率合成技術之5.2 GHz功率放大器，藉由堆疊每一功率元件的電壓，進而抬高整體的輸出電壓及功率，晶片佈局面積為1.2×1 mm2，量測增益(S21)為13.37 dB，飽和輸出功率(Psat)為27.63 dBm，1dB增益壓縮輸出功率(OP1dB)為23.45 dBm，最高功率輔助效率(PAE)為19.18%。

Recently, with the development of high-speed wireless communications, very high throughput wireless local area network (WLANs) is rising. Due to the spectrum congestion at 2.4 GHz, leading the development of circuit design towards the 5 GHz U-NII (Unlicensed National Information Infrastructure) band with unlicensed and for free. In addition, power amplifier (PA) is a key component in the RF transceiver. By and large, the radio frequency power amplifiers (RFPAs) are implemented in GaAs technology for power and efficiency. However, Complementary Metal-Oxide Semiconductor (CMOS) PA is attractive for low cost and systems-on-a-chip (SoC) applications, so the 5 GHz U-NII band CMOS PA has become a new trend. Therefore, this thesis designs and implements three 5.2 GHz CMOS PAs using different power combining techniques.
First, a 5-5.8 GHz fully-integrated single-ended PA is designed and fabricated utilizing a two-way direct shunt combining technique, the CMOS PA achieves a measured maximum saturation output power (Psat) of 23.1 dBm at 5.2 GHz. The measured output 1-dB compression point (OP1dB) is 18.6 dBm and peak power-added efficiency (PAE) is 19.8 % at 5.2 GHz. By using broadband power matching topology, the output power of the CMOS PA is 22.6 ± 0.5 dBm from 5 to 5.8 GHz.
And then, a 5.2 GHz differential PA with transformer power combining technique has been designed and implemented. The PA demonstrates a Psat of 25.81 dBm, OP1dB of 21.42 dBm and peak PAE of 27.58 % at 5.2 GHz.
Finally, for higher output power application, a 5.2 GHz 0.5 watt CMOS PA using series combining transformer to accumulate the voltage of each power device for boosting the output voltage and power has been designed and fabricated. The PA demonstrates a Psat of 27.63 dBm, OP1dB of 23.45 dBm with peak PAE of 19.18 % at 5.2 GHz.

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