在數位傳播衛星(DBS)的規範下，操作在Ku頻帶10.7~12.75GHz的低雜訊模塊降頻器是衛星電視訊號接收鏈中一個重要的部份。因為低雜訊模塊降頻器必需將Ku-Band的RF訊號降頻至L-Band的IF訊號(0.95~2.15GHz)。因此在低雜訊模塊降頻器的設計上，需要一個X頻帶頻率合成器來提供9.75GHz及10.6GHz的振盪源訊號。本論文使用了TSMC CMOS 0.18-µm製程實現了X頻段9.75/10.6GHz頻率合成器。
本論文依序實現了多模除頻器、X頻帶頻率合成器前端電路以及X頻帶9.75/10.6GHz頻率合成器，分別在第三章、第四章及第五章呈現。在第三章實現出了一個七位元多模除頻器，其除數從128~255，在直流偏壓1.5V下最高可操作在3.3GHz，功率消耗為5.85mW。在第四章實現了X頻帶頻率合成器前端電路，包含電壓控制振盪器及除四預除頻器電路兩個部份。電壓控制振盪器部份採用交叉耦合對的方式，同時利用一個開關電路來實現9.75/10.6 GHz頻段切換的功能。其功率消耗為10.5mW。高頻頻段相位雜訊在載波偏移1MHz處-102.95dBc/Hz；低頻頻段相位雜訊在載波偏移1MHz處為-92.199dBc/Hz。預除頻電路部分採用電流模式邏輯式的除頻器架構。同時，刪除了CML的尾電流部分來增加速度。其功率消耗為14.5mW。在第五章實現了X頻帶9.75/10.6GHz頻率合成器。輸出頻率為9.75GHz時，相位雜訊在載波偏移100KHz處為-66.11 dBc/Hz；在載波偏移1MHz處為-89.85 dBc/Hz。輸出頻率為10.6GHz時，相位雜訊在載波偏移100KHz處為-66.77 dBC/Hz；在載波偏移1MHz處為-90.55 dBC/Hz。其功率消耗為34.5mW。

Under Digital Broadcast Satellite (DBS) regulations, Low Noise Block (LNB) down-converter operated in Ku-band 10.7~12.75 GHz is an important part of the satellite- TV reception chain. Because LNB down-converter is in charge of converting the Ku-band RF signal down to L-band IF signal (0.95~2.15GHz), the X-band frequency synthesizers is necessary block in LNB system design to provide 9.75GHz and 10.6GHz local oscillator (LO). In this thesis, a X-band 9.75/10.6 GHz Frequency Synthesizer is presented by using TSMC CMOS 0.18-µm process.
This thesis implemented 7-bits Multi-Modulus Divider, X-band synthesizer frontend circuit and X-band 9.75/10.6 GHz frequency synthesizer in chapter 3, chapter 4 and chapter 5, respectively. In chapter 3, 7-bits Multi-Modulus Divider is presented, which divisor are 128~255 and highest operating frequency is 3.3 GHz in 1.5V.Multi-Modulus divider power consumption is 5.85 mW. In chapter 4, X-band synthesizer frontend circuit, included VCO and ÷4 prescalar, is presented. The VCO employs LC-tank cross-coupled pair architecture. In order to switch frequencies between the 9.75 GHz and 10.6 GHz, VCO specially use a switch circuit. VCO power consumption is 10.5 mW. When VCO in high band, phase noise is -102.95 dBc/Hz@1MHz. In low band, phase noise is -92.19 dBc/Hz@1MHz. The ÷4 prescalar circuit employs CML architecture. For promoting the speed, tail-current of CML Divider are removed.CML power consumption is 14.5 mW. In chapter 5, X-band 9.75/10.6 GHz frequency Synthesizer is presented. When output frequency in 9.75 GHz, phase noise are -66.11 dBc/Hz@100KHz and -89.85 dBc/Hz@1MHz. When output frequency in 10.6 GHz, phase noise are -66.77 dBc/Hz@100KHz and -90.55 dBc/Hz@1MHz. X-band Frequency Synthesizer power consumption is 34.5mW.

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