本論文提出了一種應用於寬頻積體電路之全晶片靜電放電防護設計，在0.18μm CMOS製程下，以矽控整流器元件搭配分散式電路的設計，並與既有二極體元件的設計相比較。
當內部電路的操作頻率上升，寄生電容造成的訊號損耗也益加嚴重，單級的靜電放電防護設計不再適用於高頻電路，為了維持原有的防護效果，本論文提出π型架構的設計，將單級的防護元件以小尺寸分散至兩級，藉由匹配元件的使用，來降低訊號通過時的損耗，傳統的π型架構設計使用的是二極體元件，本論文則是採用矽控整流器元件搭配π型架構，矽控整流器在單位面積下具有高的靜電放電耐受度，藉由二極體串的觸發，導通速度得以提升，並藉由電感的使用來達到良好的寬頻表現。
最後，將傳統二極體設計與本設計應用於K波段下的低雜訊放大器，透過電路的量測結果，驗證對電路的影響與實際的防護效果。

This thesis proposed a whole-chip electrostatic discharge (ESD) protection design for broadband circuits. In 0.18μm CMOS process, the silicon-controlled rectifier (SCR) is designed with distributed circuit in comparison with traditional design by diode.
As the operating frequency of IC increases, the signal loss caused by ESD protection device is more severe. The ESD protection design with one stage is no longer suitable for high-frequency applications. π-model structure is proposed to solve this problem. The device is divided into two sections. Two parts are connected with an inductor. By the use of matching element, the signal loss is reduced. Traditional π-model structure is realized with diode. This thesis proposed a π-model design with SCR. SCR has great ESD robustness per unit area. With the trigger diodes, the turn-on efficiency of SCR can be improved. With the help of matching inductor, the broadband performance is maintained. Traditional design and proposed design are realized with K-band low-noise amplifier (LNA) to learn the protective effect.

[1] S. H. Voldman, ESD Physics and Devices. New York: Wiley, 2005.
[2] O. Semenov et al., ESD Protection Devices and Circuit Design for Advanced CMOS Technologies. Amsterdam: Springer, 2008.
[3] T. Lim et al., “Geometrical impact on RF performances of broadband ESD self-protected transmission line in advanced CMOS technologies,” in Proc. IEEE International Integrated Reliability Workshop, Oct. 2012, pp. 14-18.
[4] ESD Association and JEDEC Solid State Technology Association, “Human body model (HBM) - component level,” ANSI/ESDA/JEDEC JS-001-2017, 2017.
[5] Microelectronics Test Method Standard MIL-STD-883D Method 301 5.7, “Electrostatic discharge sensitivity classification,” US Department of Defense, 1991.
[6] Industry Council on ESD Target Levels, “White Paper 1: A case for lowering component level HBM/MM ESD specifications and requirements,” Sep. 2011.
[7] E. Grund et al., “A new CDM discharge head for increased repeatability and testing small pitch packages,” in Proc. EOS/ESD Symposium, 2018.
[8] ESD Association and JEDEC Solid State Technology Association, “Charged device model (CDM) - component level,” ANSI/ESDA/JEDEC JS-002-2014, 2014.
[9] W.-Y. Chen et al., “Diode-triggered silicon-controlled rectifier with reduced voltage overshoot for CDM ESD protection,” IEEE Transactions on Device and Material Reliability, vol. 12, no. 1, pp. 10-14, Mar. 2012.
[10] Industry Council on ESD Target Levels, “White Paper 2: A case for lowering component level CDM ESD specifications and requirements,” Apr. 2010.
[11] “Electrostatic Discharge (ESD) in 3D-IC Packages,” GSA white paper, Version 1.0, Jan. 2015.
[12] G. Boselli et al., “Analysis of ESD protection components in 65-nm CMOS technology: Scaling perspective and impact on ESD design windows,” in Proc. EOS/ESD Symposium, 2005, pp. 43-52.
[13] A. Amerasekera and C. Duvvury, ESD in Silicon Integrated Circuits. New York: Wiley, 1995.
[14] M.-D. Ker and C.-Y. Lin, “Low-capacitance SCR with waffle layout structure for on-chip ESD protection in RF ICs,” IEEE Transactions on Microwave Theory and Techniques, vol. 56, no. 5, pp. 1286-1294, Mar. 2008.
[15] K. Shrier et al., “Transmission line pulse test methods, test techniques and characterization of low capacitance voltage suppression device for system level electrostatic discharge compliance,” in Proc. EOS/ESD Symposium, 2004.
[16] D. Abessolo-Bidzo and E. Thomas, “Circuit under pad active bipolar ESD clamp for RF applications,” in Proc. EOS/ESD Symposium, 2017, pp. 1-7.
[17] C.-Y Lin et al., “ESD protection design for gigahertz differential LNA in a 65-nm CMOS process,” in Proc. Asia-Pacific International Symposium on Electromagnetic Compatibility, 2015.
[18] A. Y. Ginawi et al., “Investigation of diode triggered silicon control rectifier turn-on time during ESD events,” in Proc. IEEE System-on-Chip Conference, 2017, pp. 5-8.
[19] M.-D. Ker and K.-C. Hsu, “Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits,” IEEE Transactions on Devices and Materials Reliability, vol. 5, no. 2, pp. 235-249, Jun. 2005.
[20] N. Jack and E. Rosenbaum, “ESD protection for high-speed receiver circuits,” in Proc. IEEE International Reliability Physics Symposium, 2010, pp. 835-840.
[21] M.-D. Ker and C.-Y. Chang, “ESD protection design for CMOS RF integrated circuits using polysilicon diodes,” Microelectronics Reliability, vol. 42, no. 6, pp. 863-872, Jun. 2002.
[22] M. P. J. Mergens et al., “Speed optimized diode-triggered SCR (DTSCR) for RF-ESD protection of ultra-sensitive IC nodes in advanced technologies,” IEEE Transactions on Device and Material Reliability, vol. 5, no. 3, pp. 532-542, Sep. 2005.
[23] C.-Y. Lin et al., “ESD protection design for 60-GHz LNA with inductor-triggered SCR in 65-nm CMOS process,” IEEE Transactions on Microwave Theory and Techniques, vol. 60, no. 3, pp. 714-723, Mar. 2012.
[24] C.-Y. Lin and R.-K. Chang, “Test structures of LASCR device for RF ESD protection in nanoscale CMOS process,” in Proc. IEEE International Conference on Microelectronic Test Structures, 2016, pp.100-103.
[25] M.-D. Ker et al., “Optimization of broadband RF performance and ESD robustness by -model distributed ESD protection scheme,” Journal of Electrostatics, vol. 64, no. 2, pp. 80-87, Feb. 2006.
[26] I. Backers et al., “Low capacitive dual bipolar ESD protection,” in Proc. EOS/ESD Symposium, 2017, pp. 1-7.
[27] A. Dong et al., “Distributed ESD protection network for millimetre-wave RF applications,” IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, 2018.
[28] T. Lim et al., “Generic electrostatic discharges protection solutions for RF and millimeter-wave applications,” IEEE Transactions on Microwave Theory and Techniques, vol. 63, no. 11, pp. 3747-3759, Nov. 2015.
[29] M.-D. Ker et al., “Overview on ESD protection designs of low-parasitic capacitance for RF ICs in CMOS technologies,” IEEE Transactions on Device and Materials Reliability, vol. 11, no. 2, pp. 207-218, Jun. 2011.
[30] M.-D. Ker and K.-C. Hsu, “Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits,” IEEE Transactions on Device and Materials Reliability, vol. 5, no. 2, pp. 235-249, Jun. 2005.
[31] D.-W. Lai et al., “DNW-Controllable triggered voltage of the integrated diode triggered SCR (IDT-SCR) ESD protection device,” in Proc. EOS/ESD Symposium, 2017.
[32] S. Cao et al., “ESD design strategies for high-speed digital and RF circuits in deeply scaled silicon technologies,” IEEE Transactions on Circuits and Systems, Part I: Regular Papers, vol. 57, no. 9, pp. 2301-2311, Sep. 2010.
[33] T.-M. Hsien et al., “An ultra-low power K-band low-noise amplifier co-designed with ESD protection in 40-nm CMOS,” in Proc. IEEE International Conference on IC Design and Technology, 2011.
[34] V. Issakov et al., “A low power 24 GHz LNA in 0.13m CMOS,” in Proc. IEEE International Conference on Microwaves, Communications, Antennas and Electronic Systems, 2008, pp. 1-10.
[35] D. Linten et al., “A 4.5 kV HBM, 300 V CDM, 1.2 kV HMM ESD protected DC-to-16.1 GHz wideband LNA in 90 nm CMOS,” in Proc. EOS/ESD Symposium, 2009, pp. 352-357.