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研究生： 魏文港
Wen-Kang , Wei
論文名稱： 於可程式化系統晶片平台實現向量量化器快速碼字搜尋硬體電路之研究
Fast Codeword Search Algorithm for Vector Quantization on System-on-Programmable-Chip Development Platform
指導教授： 黃文吉
Hwang, Wen-Jyi
學位類別： 碩士
Master
系所名稱： 資訊工程學系
Department of Computer Science and Information Engineering
論文出版年： 2005
畢業學年度： 93
語文別： 中文
論文頁數： 47
中文關鍵詞： 向量量化器 、部分距離搜尋 、最佳碼字搜尋 、子空間搜尋 、位元平面縮減 、多係數累積
英文關鍵詞： Vector Quantier, Partial Distance Search, Subspace search, Bitplane reduction, Multiple-coefficient accumulation
論文種類： 學術論文
相關次數： 點閱：136  下載：4 
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    • 本論文針對向量量化器（VQ）編碼端的硬體實現提出了一個新的VLSI架構，採用部分距離搜尋（PDS）演算法作為編碼端最佳碼字搜尋的法則。在大多數的軟體應用中，部份距離搜尋演算法可以適度的加速碼字搜尋。本論文提出的新部份距離搜尋演算法適合硬體實現，使用子空間搜尋（Subspace search）、位元平面縮減（Bitplane reduction）和多係數累積（Multiple-coefficient accumulation）三種技術來有效的降低面積複雜度（Area complexity）以及計算latency（Computation latency）。多模組架構的PDS專用硬體電路可以同時針對不同的輸入向量進行編碼，以達到更進一步的編碼加速。我們提出的硬體架構被內嵌於軟體核心中央處理器（Softcore CPU）來進行實際的效能量測。實驗結果顯示出我們的架構提供了一個符合成本效益的向量量化器編碼系統硬體實作解決方案，並且擁有高吞吐量（throughput）和高正確性（fidelity）。

    This paper presents a novel VLSI architecture for hardware realization of vector quantizer (VQ) encoders using partial distance search (PDS). In most applications, the PDS is adopted as a software approach for attaining moderate codeword search acceleration. In this paper, a novel PDS algorithm well-suited for hardware realization is proposed. The algorithm employs subspace search, bitplane reduction and multiple-coefficient accumulation techniques for the effective reduction of the area complexity and computation latency. Concurrent encoding of different input vectors for further encoding acceleration are also allowed by the employment of multiple-module PDS. The proposed architecture has been embedded in a softcore CPU for physical performance measurement. Experimental results shows that the architecture provides a cost-effective solution to the hardware realization of VQ encoding systems where both high throughput and high fidelity are desired.

    中文摘要…………………………………………………………i 英文摘要…………………………………………………………ii 誌謝………………………………………………………………iii 目錄………………………………………………………………iv 附圖目錄…………………………………………………………vi 附表目錄…………………………………………………………vii 第一章 緒論……………………………………………………1 1.1 研究背景與動機目的…………………………………1 1.2 全文架構………………………………………………5 第二章 基礎理論介紹…………………………………………7 2.1 向量量化器基本架構…………………………………7 2.2 離散小波轉換…………………………………………10 2.3 部分距離碼字搜尋演算法則…………………………12 第三章 PDS架構與硬體實現…………………………………16 3.1 PDS架構的硬體實現…………………………………16 3.1.1 子空間搜尋（Subspace search）………………16 3.1.2 位元平面縮減（Bitplane reduction）…………19 3.1.3 多係數部分距離累積（Multiple-coefficient partial distance acccumulation）………21 3.1.4 subspace PDS硬體實現的概述……………………24 3.2 單一模組VLSI硬體架構………………………………27 3.3 多模組VLSI硬體架構…………………………………31 3.4 內嵌於軟核心處理器的PDS使用者自訂邏輯區塊……37 第四章 實驗數據與效能比較……………………………………42 第五章 結論………………………………………………………47 參考文獻…………………………………………………………48

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