本論文研製之三個5.2 GHz功率放大器分別利用變壓器功率合成技術、電流合成變壓器技術與內建線性器技術來設計，並實現於標準0.18-μm 1P6M互補式金屬氧化物半導體製程(Standard 0.18-μm 1P6M CMOS process)中。本論文之功率放大器量測包含了S參數、連續波訊號與數位調變訊號，其中量測數位調變之特性時所打入的訊號為IEEE 802.11a WLAN之OFDM 54 Mbps 64-QAM Modulated Signal。
第一個電路為利用變壓器功率合成技術之5.2 GHz功率放大器，透過變壓器的阻抗轉換與功率結合之能力，達成輸入共軛匹配、輸出功率阻抗匹配與高輸出功率。當功率放大器的VG1分別為0.85 V與1.0 V時，其功率增益(Power gain)分別約為16.59 dB與16.27 dB，飽和輸出功率Psat分別約為24.9 dBm與24.79 dBm，1-dB增益壓縮點之輸出功率OP1dB分別約為20.3 dBm與18 dBm，靜態電流分別為218.35 mA與334.91 mA，最大功率附加效率Peak PAE分別約為28.37 %與26.46 %，整體晶片佈局面積為1.2 mm × 0.6 mm。
第二個電路為利用電流合成變壓器技術之5.2 GHz功率放大器，以利用變壓器功率合成技術之5.2 GHz功率放大器為基礎，為了得到更高的輸出功率，本電路透過電流合成變壓器技術將其輸出端做功率結合，並達到輸出功率提升近3 dBm的效果。當功率放大器的VG1分別為0.85 V與1.0 V時，其功率增益(Power gain)分別約為14.29 dB與13.48 dB，飽和輸出功率Psat分別約為27.59 dBm與27.49 dBm，1-dB增益壓縮點之輸出功率OP1dB分別約為21.43 dBm與17.96 dBm，靜態電流分別約為457.9 mA與666.61 mA，最大功率附加效率Peak PAE分別約為20.18 %與18.83 %，整體晶片佈局面積為1.2 mm × 1.15 mm。
第三個電路為具內建線性器之5.2 GHz功率放大器，以利用電流合成變壓器技術之5.2 GHz功率放大器為基礎，在其輸入端掛接一疊接組態線性器，並透過改變線性器之控制電壓Vctrl而達到控制功率放大器之線性度改善的程度。當功率放大器的VG1為1.0 V且線性器開啟時，功率增益約8.74 dB，飽和輸出功率Psat約為25.01 dBm，1-dB增益壓縮點之輸出功率OP1dB約為22 dBm，最大功率附加效率Peak PAE約為9.92 %，三階交互調變失真IMD3在輸出功率約為18 dBm以前皆可抑制在35 dBc左右，誤差向量振幅EVM在輸出功率約為16 dBm以前皆可抑制在2 %左右，當誤差向量振幅EVM約為5.6 %時所操作之輸出功率約為19 dBm，整體晶片佈局面積為1.2 mm × 1.17 mm。

In this paper, three 5.2-GHz power amplifiers are presented, which were separately utilized the techniques of transformer power combining, current combining transformer and build-in linearizer, and implemented in 0.18-μm CMOS technology. The measurements of three power amplifiers include S-parameters, continuous wave signal and digital modulation signal with OFDM 54 Mbps 64-QAM of IEEE 802.11a WLAN.
First, a 5.2 GHz power amplifier with transformer power combining technique has been designed and implemented. To achieve input impedance matching, output power matching and high output power, we utilize the transformer to implement the impedance conversion and the power combining. When the VG1 of the power amplifier operating in 0.85 V, the power amplifier exhibits the power gain of 16.59 dB, the saturated output power of 24.9 dBm, the output power of 20.3 dBm at 1-dB compression point, the quiescent current of 218.35 mA and the maximum power added efficiency of 28.37 %. When the VG1 of the power amplifier operating in 1.0 V, the power amplifier exhibits the power gain of 16.27 dB, the saturated output power of 24.79 dBm, the output power of 18 dBm at 1-dB compression point, the quiescent current of 334.91 mA and the maximum power added efficiency of 26.46 %.The chip size is 1.2 mm × 0.6 mm.
Second, based on the 5.2 GHz power amplifier with transformer power combining technique, a 5.2 GHz power amplifier with current combining transformer technique has been designed and implemented. To achieve the higher output power, current combining transformer technique is adopted. When the VG1 of the power amplifier operating in 0.85 V, the power amplifier demonstrates the power gain of 14.29 dB, the saturated output power of 27.59 dBm, the output power of 21.43 dBm at 1-dB compression point, the quiescent current of 457.9 mA and the maximum power added efficiency of 20.18 %. When the VG1 of the power amplifier operating in 1.0 V, the power amplifier demonstrates the power gain of 13.48 dB, the saturated output power of 27.49 dBm, the output power of 17.96 dBm at 1-dB compression point, the quiescent current of 666.61 mA and the maximum power added efficiency of 18.83 %.The chip size is 1.2 mm × 1.15 mm.
Finally, based on the 5.2 GHz power amplifier with current combining transformer technique, a built-in linearizer utilizing cascode configuration for 5.2 GHz power amplifier has been designed and implemented. The proposed linearization technique which is shunted in the front end of the second circuit aims to control the improvement of the linearity of the power amplifier by the Vctrl. After linearization with the VG1 of the power amplifier operating at 1.0 V, the power amplifier demonstrates the power gain of 8.74 dB, the saturated output power of 25.01 dBm, the output power of 22 dBm at 1-dB compression point and the maximum power added efficiency of 9.92 %. Third-order intermodulation distortion can be suppressed below to 35 dBc until the output power of 18 dBm. Error vector magnitude can be suppressed below to 2% until the output power of 16 dBm. The output power can be achieved to 19 dBm when the error vector magnitude is around the restriction of IEEE 802.11a WLAN standard of 5.6 %. The chip size is 1.2 mm × 1.17 mm.

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