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| 研究生： |
鄭博升 Cheng, Po-Sheng |
|---|---|
| 論文名稱： |
以矩陣乘法為基礎應用硬體加速器於一維卷積計算之研究 Matrix multiplication based 1-D convolution with hardware accelerator |
| 指導教授： |
黃文吉
Hwang, Wen-Jyi |
| 口試委員： |
鮑興國
Pao, Hsing-Kuo 葉佐任 Yeh, Tso-Zen 黃文吉 Hwang, Wen-Jyi |
| 口試日期： | 2022/07/27 |
| 學位類別： |
碩士 Master |
| 系所名稱： |
資訊工程學系 Department of Computer Science and Information Engineering |
| 論文出版年： | 2022 |
| 畢業學年度： | 110 |
| 語文別： | 中文 |
| 論文頁數： | 51 |
| 中文關鍵詞： | 矩陣乘法 、卷積計算 、類神經網路 、硬體加速器 、量化 |
| 英文關鍵詞： | FPGA, Quantization, Systolic Array, Weight Stationary |
| 研究方法: | 實驗設計法 |
| DOI URL： | http://doi.org/10.6345/NTNU202201331 |
| 論文種類： | 學術論文 |
| 相關次數： | 點閱：109 下載：8 |
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隨著電腦計算能力的提升，人工智慧得以受惠於大量的卷積計算來取得資料的特徵，使電腦可以幫我們處理各種複雜的任務。在提升卷積計算的速度的研究中，以矩陣乘法來實作卷積計算是常見的一種方式。
本論文針對一維的卷積計算，提出一種矩陣排列的方式，將一維卷積計算得以用矩陣乘法來達成，並且進一步的使用通用型硬體加速器，來大幅提升矩陣乘法的計算效能。
將本論文的方法應用於神經網路模型，並佈署在FPGA開發版上，經過實驗的驗證，我們可以精準的產出計算結果，並且加速整體神經網路模型的計算效能。
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