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研究生： 劉家凱
Liu, Chia-Kai
論文名稱： K頻帶互補式金氧半功率放大器設計
Design of K-band CMOS Power Amplifiers
指導教授： 蔡政翰
Tsai, Jen-Han
學位類別： 碩士
Master
系所名稱： 電機工程學系
Department of Electrical Engineering
論文出版年： 2015
畢業學年度： 103
語文別： 中文
論文頁數： 93
中文關鍵詞： K頻段 、功率放大器 、變壓器 、互補式金屬氧化半導體 、功率合成技術
英文關鍵詞： K-band, power amplifier, transformer, CMOS, power combining techniques
論文種類： 學術論文
相關次數： 點閱：139  下載：7 
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    • 第一個電路為變壓器功率結合技術之K頻帶功率放大器，採用半圈變壓器 (Half-turn Transformer)實現功率結合與阻抗轉換以達到節省面積，量測結果在23.5 GHz時，增益為12 dB，飽和輸出功率(P_sat)為22.5 dBm，1dB增益壓縮輸出功率(OP_1dB)為18.1 dBm，最高功率輔助效率(PAE)為21.8%，晶片佈局面積為0.29 mm^2。
    第二個電路為變壓器電流結合技術之K頻帶功率放大器，延續第一個設計之功率放大器，運用變壓器電流結合技術(Current Combining Transformer)來提升輸出功率，將功率放大單元直接並聯在進行匹配，而為了要提高增益，採用兩級功率放大器進行設計，量測結果在23 GHz時，增益為19.5 dB，飽和輸出功率(P_sat)為24.9 dBm，1 dB增益壓縮輸出功率(OP_1dB)為20.6 dBm，最高功率輔助效率(PAE)為17.0%，晶片佈局面積為0.97 mm^2。

    The first circuit is K-band power amplifier with transformer combining technique which uses half-turn transformer to implement power combining and impedance transformations, and to reduce size of chip. The PA achieves measured small-signal gain ("S" _"21" ) of 12 dB and maximum saturation output power ("P" _"sat" ) of 22.5 dBm, the measured output 1-dB compression point (〖"OP" 〗_"1dB" ) of 18.1 dBm and peak power-added efficiency (PAE) is 21.8 % at 23.5 GHz. The chip area is 0.29 mm^2.
    Recall that in first design, the second circuit is power amplifier using current combining transformer technique to increase output power. In order to reach higher gain, this thesis use 2-stage power amplifier design. The PA achieves measured "S" _"21" of 19.5 dB and "P" _"sat" of 24.9 dBm, the 〖"OP" 〗_"1dB" of 20.6 dBm and PAE of 17 % at 23 GHz. The chip area including is 0.97 mm^2.

    摘 要 i ABSTRACT iii 誌謝 v 目 錄 vii 圖 目 錄 xi 表 目 錄 xvii 第一章 緒論 1 1.1 研究背景與動機 1 1.2 文獻探討 2 1.3 研究成果 4 1.4 論文架構 4 第二章 功率放大器之介紹 7 2.1 概述 7 2.2 功率放大器之重要參數 8 2.2.1 功率(Power) 8 2.2.2 效率(Efficiency) 9 2.2.3 線性度(Linearity) 9 2.3 功率放大器種類 15 2.3.1 A類(Class A)功率放大器 16 2.3.2 B類(Class B)功率放大器 17 2.3.3 AB類(Class AB)功率放大器 18 2.3.4 C類(Class C)功率放大器 19 第三章 Half-turn變壓器功率結合技術之K頻帶功率放大器 21 3.1 簡介 21 3.2 變壓器功率結合技術之K頻帶功率放大器設計 22 3.2.1偏壓分析與選擇 22 3.2.2組態選擇 24 3.2.3電晶體元件尺寸分析及選擇 25 3.2.4 變壓器原理 28 3.2.5 輸出匹配網路設計 29 3.2.6 輸入匹配網路設計 41 3.2.7 旁路電路設計 47 3.3 模擬結果 49 3.4 量測結果 52 3.5 問題與討論 58 3.5.1 相位差問題 58 3.6 總結 59 第四章 變壓器電流結合技術之K頻帶功率放大器 61 4.1 簡介 61 4.2 變壓器電流結合技術之K頻帶功率放大器設計 62 4.2.1 變壓器電流結合技術效率 62 4.2.2 輸出匹配網路設計 64 4.2.3 級間匹配網路設計 71 4.3 模擬結果 73 4.4 量測結果 78 4.6 總結 84 第五章 結論 87 參 考 文 獻 89 自傳 93 學術成就 93

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