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研究生： 林煜哲
Lin, Yu-Zhe
論文名稱： 應用於第五代行動通訊之28 GHz與38 GHz之功率放大器研究
Research on 28 GHz and 38 GHz Power Amplifiers for Fifth Generation Wireless Communication System
指導教授： 蔡政翰
Tsai, Jen-Han
學位類別： 碩士
Master
系所名稱： 電機工程學系
Department of Electrical Engineering
論文出版年： 2017
畢業學年度： 105
語文別： 中文
論文頁數： 133
中文關鍵詞： Ka頻帶 、功率放大器 、變壓器 、功率合成技術 、互補式金氧半
英文關鍵詞： Ka-band, power amplifier, transformer, power combining techniques, CMOS
DOI URL： https://doi.org/10.6345/NTNU202202536
論文種類： 學術論文
相關次數： 點閱：126  下載：5 
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    • 第一個電路為利用變壓器功率合成技術之Ka頻帶之功率放大器，使用半圈之變壓器實現功率結合與阻抗轉換以達到節省晶片面積，在量測頻率28 GHz時，增益為10.13 dB，飽和輸出功率為21.69 dBm，OP1dB為16.48 dBm，最大功率附加效率Peak PAE為19.36 %，整體晶片佈局面積為0.29 mm2。
    第二個電路為變壓器電流合成技術之Ka頻帶功率放大器，為了提升功率放大器的增益，採用二級功率放大器進行設計，再使用變壓器電流合成技術提升輸出功率，量測結果在28 GHz時增益為14.07 dB，飽和輸出功率為23.9 dBm，OP1dB為19.07 dBm，最高功率附加效率為13 %，晶片佈局面積為0.9 mm2。
    第三個電路為利用直接並聯功率合成瓦級功率輸出之Ka頻帶功率放大器，為了達到高增益，透過三級放大器進行設計，並使用直接並聯功率合成提升輸出功率，量測結果在38GHz時增益為19.6 dB，飽和輸出功率為28.4 dBm，OP1dB為27.6 dBm，最高功率附加效率為22.92 %，整體晶片佈局面積為5.22 mm2。

    The first circuit is Ka-band power amplifier with transformer combining technique which use half-turn transformer to implement power combining and impedance transformations, and to reduce size of chip. The PA achieves measured small-signal gain (S21) of 10.13 dB and maximum saturation output power (Psat) of 21.69 dBm, the OP1dB of 16.48 dBm and peak power-added efficiency (PAE) is 19.36 % at 28 GHz. The chip area including is 0.29 mm2.
    The second circuit is Ka-band power amplifier using current combining transformer technique. In order to reach higher gain, this thesis use 2-stage power amplifier design, and use current combining technique to increase output power. The PA achieves measured S21 of 14.07 dB and Psat of 23.9 dBm, the OP1dB of 19 dBm and PAE of 13 % at 28 GHz. The chip area including is 0.9 mm2.
    The third circuit is Ka-band power amplifier using directly power combining technique. In order to reach higher gain, this thesis use 3-stage power amplifier design, and use directly power combining technique to increase output power. The PA achieves measured S21 of 19.6 dB and Psat of 28.4 dBm, the OP1dB of 27.6 dBm and PAE of 22.92 % at 238 GHz. The chip area including is 5.22 mm2.

    摘要 I All ABSTRACT III 致謝 V 目錄 VII 圖目錄 XI 表目錄 XVII 第一章 緒論 1 1.1 研究背景與動機 1 1.2 文獻探討 1 1.3 研究成果 4 1.4 論文架構 5 第二章 功率放大器基本介紹 7 2.1 概述 7 2.2 功率放大器之重要設計參數 8 2.2.1 功率(Power) 8 2.2.2 效率(Efficiency) 9 2.2.3 線性度(Linearity) 9 2. 3 功率放大器種類 14 2.3.1 A類功率放大器(Class-A) 15 2.3.2 B類功率放大器(Class-B) 16 2.3.3 C類功率放大器(Class-C) 18 第三章 Half-turn變壓器功率結合技術之Ka頻帶功率放大器 19 3.1 簡介 19 3.1 變壓器功率結合技術之Ka頻帶功率放大器 20 3.2.1 偏壓分析與選擇 20 3.2.2 組態選擇 22 3.2.3 電晶體尺寸分析與選擇 23 3.2.4 變壓器原理 27 3.2.5 輸出匹配網路設計 28 3.2.6 輸入匹配網路設計 38 3.2.7 旁路電容設計 43 3.3 模擬結果 46 3.4 功率放大器之量測結果 49 3.5 總結 54 第四章 變壓器電流結合技術之Ka頻帶功率放大器 57 4.1 簡介 57 4.2 變壓器電流合成技術之Ka頻帶功率放大器設計 58 4.2.1 變壓器電流合成技術效率 58 4.2.2 驅動級設計 60 4.2.3 級間匹配網路設計 67 4.2.4 變壓器電流合成技術之功率放大器輸出匹配網路設計 69 4.2.5 變壓器電流合成技術之功率放大器輸出匹配網路設計 75 4.3 模擬結果 83 4.4 功率放大器之量測結果 87 4.6 總結 91 第五章 38GHz 瓦級功率輸出三級功率放大器設計 93 5.1 簡介 93 5.2 38GHz 瓦級功率輸出三級功率放大器設計 94 5.2.1 偏壓分析與選擇 94 5.2.2 電晶體尺寸分析與選擇 96 5.2.3 匹配網路設計 100 5.2.4 旁路電容設計 106 5.3 模擬結果 108 5.4 功率放大器之量測結果 111 5.5 問題與討論 119 5.6 總結 123 第六章 結論 125 參考文獻 127 自傳 133 學術成就 133

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