本研究主要針對具接觸孔蝕刻停止層 (contact etch stop layer, CESL) 之n型電晶體結構進行分析，並探討其材料及結構尺寸對元件應力分佈與性能之影響。由於CESL能提升電晶體元件之效能，為探討其結構影響之顯著性，本研究將CESL區分成三個部位，分別為CESL-Top、CESL-Lateral及CESL-Bottom三個區域，探討其結構之間傳遞應力與互相影響的情形，針對材料比例作模擬設計，並比較通道區域的應力分佈。
本論文分為三個研究方向，分別為CESL區分為三個區塊之影響研究、在覆蓋CESL層下之spacer影響研究以及在覆蓋CESL層下之電晶體尺寸影響研究。為了改善結構中間接效應的影響，在設計結構中，以區域結構分別建立，並在部分結構中施加應力的方式去探討，在n型電晶體中覆蓋1 GPa之CESL拉伸應力，而在改變閘極長度時，使得接觸CESL所覆蓋的區域也會跟著變動，可以隨著分析圖示中看出力量的分佈情形。首先，本文以2D模擬與文獻作比較，確定通道區域在z方向發生結構間的間接效應影響後，便以3D模擬設計去改善間接效應所帶來的應力現象，結果也發現在短通道時，CESL-Bottom區域能提供在通道中x方向最為顯著的影響。
另一方面，在電晶體製程的側壁結構 (spacer) 也是擔任傳遞力量的重要角色，在側壁結構內側的氧化層也常因為尺寸過小而被忽略，本研究設計二氧化矽層與氮化矽層之間的結構比例，觀察其CESL傳遞力量至通道間的影響情形，本研究考慮元件佈局圖對於電晶體之應力分佈與性能表現之影響，以二維與三維有限元素分析，發現在二氧化矽層與氮化矽層之間比例為1:3時，CESL傳遞應力至通道中開始出現有效的提升，而在短通道中也有更明顯的表現。因此，針對短通道結構設計，若適度調整spacer結構中較低楊氏係數的材料比例，便能於通道區域產生機械應力，其能有效的改善電晶體性能。

In this study, the effect of structure size of the n-type metal-oxide field-effect transistors (NMOSFET) with contact etching stop layer (CESL) for the stress distribution and performance was analyzed. The strain nitride capping layer (CESL) was used as a stress booster improving the performance of transistors. The stress in channel region for various parts of CESL (CESL-top, CESL-lateral, CESL-bottom) were compared. It kept the whole CESL but to take into account intrinsic stress only in one CESL zone, the other two zones were stress free. The indirect effect was defined as the impact of a CESL zone in interaction with two other CESL zones. In this research, the NMOSFET was combined CESL tensile stressor and equalled to 1GPa. The result of simulation explained how the CESL transmitted the intrinsic stress to the channel. It indicated that the nitride capping layer CESL provided enough channel stresses in the short channel. The CESL-bottom had more obvious influence on the CESL-classical. The range of CESL-bottom can also be adjusted to improve the performance.
On the other hand, the strained-Si approach to enhance the channel stress induced by the CESL stressor using a spacer material between SiN and oxide had been demonstrated. We used finite element analysis (FEA) process to investigate the following research. In this study, the 3D simulation can improve the indirect effect to the channel region. In particular, when the ratio of the oxide width to the composite spacer width is 1:3, the channel stress of the SiN/oxide composite spacer almost remains the same as that of the pure oxide spacer. This explains why a low Young’s modulus material of the composite spacer serves as a stress-buffer layer on a CESL stressor. Therefore, the shorter length combining a CESL can enhance the device characteristics. For a composite spacer scheme, the silicon dioxide with a relatively low young’s modulus as a stress-buffer of the spacer becomes more important for the devices with a shorter gate length. The device performance can be efficiently improved if the stress induced within the channel region can be properly modified.

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