近年來極座標發射機有關的文獻中，脈波寬度調變器(Pulse-Width Modulator, PWM)和三角積分調變器(Delta-Sigma Modulator, DSM)，皆有被提出使用在發射機前端的封包調變[1]-[4]。對於需要高解析和高線性調變器的寬頻通訊系統而言，DSM就必須提高其量化器的位元數，才能通過寬頻通訊規格，但整體發射機需要的功率放大器個數就會倍增。幸運的是，若提高PWM的操作頻率，其所造成的諧波雜訊可輕易的被後端帶通濾波器濾除，所需的功率放大器也可少於DSM。

本論文提出一個應用於封包調變之延遲鎖定迴路建構脈波寬度調變器。為了達到高解析高線性的需求，一個128個相位輸出的延遲鎖定迴路被用來組合出64種置中型脈波寬度變化。本論文提出一個循環式壓控延遲線來減少延遲元件的個數，使得所有的128個相位可以同時地輸出。藉由一個簡易計數器，我們可將所有相位分為上升區以及下降區，來產生所需的脈波寬度輸出。本論文提出之延遲鎖定迴路建構脈波寬度調變器使用台積電90奈米製程。其整體功率消耗為36.83 mW，操作頻率為92.16MHz，供應電壓為1.2V。

In recent years, the pulse-width modulation (PWM) and delta-sigma modulation (DSM) are two popular approaches used for the front-end of the envelope modulator in traditional polar transmitters[1]-[4]. For the wide bandwidth modern communications, a high resolution and high linearity of modulator is needed. So, the DSM must increase the bits of quantizer to meet the specification, but it would make the design of post-PAs difficult to be realized. Fortunately, if the operational frequency of PWM could be appropriately increased, the annoying harmonic effect would be easily attenuated by the post-bandpass filter and the number of the post-PAs is less than DSM.

This thesis presents a DLL-based PWM for the envelope modulation of polar transmitters. For the requirements of high resolution and high linearity, a 128-phase delay-locked loop is used to generate center-aligned output pulses having 64 different pulse widths for 6-bit signal input. To reduce the number of delay cells in the multi-phase DLL, a cyclic voltage controlled delay line is presented in this thesis. The 128 output phases can be simultaneously produced by the 8-delay units of VCDL. A simple counter is used to separate the output phases of DLL into rise and fall parts. The proposed DLL-based PWM is fabricated by TSMC 90nm 1P9M process. The power consumption is 36.83 mW at a 92.16 MHz input reference frequency and a supply voltage of 1.2V.

[1] L. R. Kahn, “Single-Sideband Transmission by Envelope Elimination and Restoration,” in Proc. IRE, vol. 40, no.7, pp. 803-806, Jul. 1952.
[2] Y. Wang, “An Improved Kahn Transmitter Architecture Based on Delta-Sigma Modulation,” in IEEE MTT-S International Microwave Symposium Digest, 2003, pp. 1327-1330.
[3] A. Jerng, and C. G. Sodini, “A Wideband  Digital-RF Modulator for High Data Rate Transmitters,” IEEE J. Solid-State Circuits, vol. 42, no. 8, pp. 1710-1722, Aug 2007.
[4] A. Kavousian, D. K. Su, M. Hekmat, A. Shirvani, B.A. Wooley, “A Digitally Modulated Polar CMOS Power Amplifier With a 20-MHz Channel Bandwidth,” IEEE J. Solid-State Circuits, vol. 43, no. 10, pp. 2251-2258, Oct. 2008.
[5] J. H. Chen, H. S. Yang, H.C. Lin, and Y. J. E. Chen, “A Polar-Transmitter Architecture Using Multiphase Pulsewidth Modulation,” IEEE Trans. Circuits and Syst. I. Reg. Papers, vol. 58, no. 2, pp. 244-252, Feb. 2011.
[6] J. H. Chen, H. S. Yang, and Y. J. E. Chen, “A Multi-Level Pulse Modulated Polar Transmitter Using Digital Pulse-Width Modulation,” IEEE Microw. Wireless Compon. Lett., vol. 20, No. 5, pp. 295-297 , May 2010.
[7] D. K. Su, and W. J. McFarland, “An IC for Linearizing RF Power Amplifiers Using Envelope Elimination and Restoration,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 2252-2258, Dec. 1998.
[8] P. Nagle, P. Burton, E. Heaney, and F. McGrath, “A Wide-band Linear Amplitude Modulator for Polar Transmitters Based on the Concept of Interleaving Delta Modulation,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1748-1756, Dec. 2002.
[9] P. T. M. van Zeijl, and M. Collados, “A Digital Envelope Modulator for a WLAN OFDM Polar Transmitter in 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 42, no. 10, pp. 2204-2211, Oct. 2007.
[10] A. Kavousian, D.K. Su, M. Hekmat, A. Shirvani, B.A. Wooley, “A Digitally Modulated Polar CMOS Power Amplifier With a 20-MHz Channel Bandwidth,” IEEE J. Solid-State Circuits, vol. 43, no. 10, pp. 2251-2258, Oct. 2008.
[11] M. Taromaru, N. Ando, T. Kodera, and K. Yano, “An EER Transmitter Architecture with Burst-Width Envelope Modulation Based on Triangle-Wave Comparison PWM,” in IEEE Symp. Personal Indoor and Mobile Radio Communications, 2007, pp. 1-5.
[12] J. H. Chen, H. S. Yang, and Y. J. E. Chen, “A Technique for Implementing Wide Dynamic-Range Polar Transmitters,” IEEE Trans. on Microw. Theory and Tech., vol. 58, no. 9, pp. 2368-2374, Sept. 2010.
[13] J. H. Chen,“An Efficiency-Improved Outphasing Power Amplifier Using RF Pulse Modulation,”IEEE Microw. Wireless Compon. Lett., vol. 20, Dec. 2010.
[14] J. Choi, J. Yim, J. Yang, J. Kim, J. Cha, D. Kang, D. Kim, and B. Kim, “A ΔΣ-Digitized polar RF Transmitter,” IEEE. Trans. on Microw. Theory and Tech., vol. 55, no. 12, pp. 2679-2690, Dec 2007.
[15] J. Martires, S.B. Christensen, T. Larsen, “Envelope Signal Selective Emphasis in a Polar Radio Frequency Transmitter Architecture,” IET J. Circuits, Devices & Systems, vol. 2 , no. 6, pp. 509-517, Dec 2008.
[16] W. Y. Kim, K. Y. Kim, S. T. Ryu, J. K. Jung, and C. S. Park, “1-bit and Multi-bit Envelope Delta-Sigma Modulators for CDMA Polar Transmitter,” in Asia-Pacific Microwave Conference., 2008, pp. 1.
[17] A. Frappé, A. Flament, B. Stefanelli, A. Kaiser, and A. Cathelin, “An All-Digital RF Signal Generator Using High-Speed ΔΣ Modulators,” IEEE J. Solid-State Circuits, vol. 44, no. 10, pp. 2722-2731, Oct. 2009.
[18] C. Berland, I. Hibon, J. F. Bercher, M. Villegas, D. Belot, D. Pache, and V. L. Goascoz, “A Transmitter Architecture For Nonconstant Envelope Modulation,”IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 1, pp. 13–17, Jan. 2006.
[19] R. Paul and D. Maksimovic,“Analysis of PWM Nonlinearity in Noninverting Buck–Boost Power Converters,”in Proc. 39th IEEE Annu. Power Electron. Spec. Conf., 2008, pp. 3741–3747.
[20] V. Pinon, F. Hasbani, A. Giry, D. Pache, and C. Garnier,“A Single Chip WCDMA Envelope Reconstruction LDMOS PA with 130 MHz Switched-Mode Power Supply,”in IEEE Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2008, pp. 564–56.
[21] C. H. Kuo, H. J. Lai, and M. F. Lin, “A Multi-Band Fast-Locking Delay-Locked Loop with Jitter-Bounded Feature,” IEEE Trans. on Ultrasonics, Ferroelectrics and Frequency Control, vol. 58, no. 1, pp. 51–59, Jan. 2011.
[22] R. J. Yang, K. H. Chao, and S. I. Liu, “A 200-Mbps 2-Gbps Continuous-Rate Clock-and-Recovery Circuit,” IEEE Transactions on Circuits and Systems I, vol. 53, No. 4, pp. 842-847, Apr. 2006.
[23] M. Zanuso, P. Madoglio, S. Levantino, C. Samori, and A. Lacaita, “Time-to-Digital Converter For Frequency Synthesis Based On A Digital Bang-Bang DLL”, IEEE Trans. Circuits Syst. I, vol. 57, pp. 548-555, Mar. 2010.
[24] T. T. Liu and C. K. Wang, “A 1-4 GHz DLL based low-jitter multi-phase clock generator for low-band ultra-wideband application,” IEEE Asia-Pacific Conf. on Adv. Sys. Integrated Circuits, pp. 330–333, Aug. 2004.
[25] C. K. Liang, R. J. Yang, and S. I. Liu, “An All-Digital Fast-Locking Programmable DLL-Based Clock Generator,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 1, pp. 361–369, Feb. 2008.
[26] C. N. Chuang, and S. I. Liu, “A 20-MHz to 3-GHz wide-range multiphase delay-locked loop, ” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 56, no. 11, pp. 850–854, Nov. 2009.
[27] R. J. Yang, and S. I. Liu, “A Wide-Range Multiphase Delay-Locked Loop Using Mixed-Mode VCDLs,” IEICE Trans. Electronics, vol.E88-C, pp.1248.
[28] J. Christiansen, “An Integrated High Resolution CMOS Timing Generator Based On An Array of Delay Locked Loops,” IEEE J. Solid-State Circuits, vol. 31, no. 7, pp. 952–957, Jul. 1996.
[29] S. C. Lin and T. C. Lee, “An 833-MHz 132-phase Multiphase Clock Generator with Self-Calibration Circuits,” in Proc. IEEE Asian Solid State Circuits Conf., 2008, pp. 437–440.
[30] H. H. Chang and S. I. Liu, “A Wide-Range and Fast-Locking All-Digital Cycle-Controlled Delay-Locked Loop,” IEEE J. Solid-State Circuits, vol. 40, no. 3, pp. 661–670, Mar. 2005.
[31] T. Y. Wang, S. M. Lin, and H. W. Tsao, “Multiple Channel Programmable Timing Generators with Single Cyclic Delay Line,” IEEE Transactions on Instrumentation and Measurement, VOL. 53, NO. 4, August 2004.
[32] Y. S. Kim, S. J. Park, Y. S. Kim, D. B. Jang, S. W. Jeong, H. J. Park, and J. Y. Sim, “A 40-to-800 MHz locking multi-phase DLL,” in IEEE Int. Solid-State Circuits Conf. 2007 Dig. Tech Papers, Feb. 2007, pp. 306–307.
[33] J. M. Chou, Y. T. Hsieh, and J. T. Wu, “Phase averaging and interpolation using resistor strings or resistor rings for multi-phase clock generation,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 5, pp. 984–991, May 2006.
[34] C. H. Kuo and C. D. Jhang, “A Center-Aligned Digital Pulse-Width Modulator for Envelope Modulation of Polar Transmitters,” in Proc. IFIP/IEEE VLSI-SoC, Oct. 2013, pp.386 - 389.
[35] M. G. John and E. L. Hudson, “A variable delay line PLL for CPU-coprocessor synchronization, ” IEEE J. Solid-State Circuits, vol. 23, no. 5, pp. 1218-1223, Oct. 1998.
[36] T. H. Su, “Design of a CMOS Delay-Locked Loop based programmable frequency multiplier,” Master Thesis, National Dong-Hwa University, July. 2005.
[37] J. G. Maneatis, “Low-jitter process-independent DLL and PLL based on self-bias techniques,” IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1723-1732, Nov. 1996.
[38] H. H. Chang, J. W. Lin, and S. I. Liu, “A wide-range delay-locked loop with a fixed latency of one clock cycle,” IEEE J. Solid-State Circuits, vol. 37, no.8 , pp. 1021-1027, Aug. 2002.
[39] 廖述立, Design and Implementation of the Envelope Delta-Sigma Modulator for Multi-Mode Polar-Transmitters, 國立臺灣師範大學應用電子科技研究所碩士論文, 2012.