本論文研究內容為實現兩顆應用於第五代行動通訊系統之升頻混頻器，皆使用TSMC 65nm CMOS製程，設計頻段皆為38 GHz，此為第五代行動通訊極有可能在未來開放的頻段之一，第二章會大致介紹混頻器的主要參數和設計時的參考公式，第三章與第四章分別針對兩顆混頻器做製作過程的描述與特性分析。
第一顆晶片整體面積為0.58 mm × 0.57 mm，使用Fundamental架構並加上LO端線性提升技術(Local Oscillator boosting linearization technique)來研究其功效，中心頻率為38 GHz，在LO驅動功率9 dBm與0.5 V的閘極偏壓下，轉換增益(Conversion Gain)為-8.4 dB，OP1dB(Output Power 1 dB compression point)為-1.5 dBm，在RF(Radio frequency)頻率31-41 GHz間，當LO輸入功率為6 dBm時，轉換增益範圍為-10.4 dB到-11.3 dB間，直流功耗為0 mW。
第二顆晶片整體面積為0.82 mm × 0.52 mm，使用Sub-Harmonic架構並加上LO端線性提升技術來研究其功效，中心頻率為38 GHz，在LO驅動功率10 dBm與0.0 V的閘極偏壓和0.25 V的可變電容偏壓下，轉換增益為-10.4 dB，OP1dB為-9.3 dBm，在RF頻率29-40 GHz間，當LO輸入功率為10 dBm時，轉換增益範圍為-10.5 dB到-10.1 dB，直流功耗為0 mW。

The research of this thesis is based on two up-converter mixers. Both were fabricated using TSMC 65nm CMOS for 38 GHz applications. In the second half of this thesis, we introduce the design and implementation of mixers. Then, we express the design flow and analysis.
The chip size of the first circuit is 0.58 mm × 0.57 mm. The mixer is based on the fundamental topology with the local oscillator boosting linearization technique. This mixer provides -8.4 dB conversion gain with -1.5 dBm OP1dB(Output Power 1 dB compression point) at 38 GHz under 9 dBm LO(Local Oscillator) drive power. The bias-gate voltage is 0.5 V. The conversion gain is within the range of -10.4 to -11.3 dB with 31 to 41 GHz when LO power is 6 dBm. The dc power consumption is zero.
The chip size of the second circuit is 0.82 mm × 0.52 mm. The mixer is based on a sub-harmonic topology with LO boosting linearization technique. This mixer provides -10.4 dB conversion gain with -9.3 dBm OP1dB at 38 GHz under 10 dBm LO drive power. The bias-gate voltage is 0.0 V and the voltage of varactor is 0.25 V. The conversion gain is within the range of -10.5 to -10.1 dB with 29 to 40 GHz when LO power is 10 dBm. The dc power consumption is zero.

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