本論文研製之三個5.3 GHz功率放大器分別利用變壓器功率合成技術、電流合成變壓器技術與內建線性器技術來設計，並實現於標準0.18-μm 1P6M互補式金屬氧化物半導體製程(Standard 0.18-μm 1P6M CMOS process)中。本論文之功率放大器量測包含了S參數與連續波訊號。
第一個電路為利用變壓器功率合成技術之5.3 GHz功率放大器，透過變壓器的阻抗轉換與功率結合之能力，達成輸入共軛匹配、輸出功率阻抗匹配與高輸出功率。當功率放大器的Vg1為0.85 V時，其功率增益(Power gain)約為18.19 dB，飽和輸出功率Psat約為26.10 dBm，1-dB增益壓縮點之輸出功率OP1dB約為21.20 dBm，靜態電流約為294.60 mA，最大功率附加效率Peak PAE約為21.30 %，整體晶片佈局面積為1.17 mm × 0.64 mm。
第二個電路為利用電流合成變壓器技術之5.3 GHz功率放大器，以第一個電路為基礎，為了得到更高的輸出功率，我們透過電流合成變壓器技術將其輸出端做功率結合，並達到輸出功率提升近3 dBm的效果。當功率放大器的Vg1為0.85 V時，其功率增益(Power gain)約為16.43 dB，飽和輸出功率Psat分別約為29.43 dBm，1-dB增益壓縮點之輸出功率OP1dB約為25.44 dBm，靜態電流約為610.50 mA，最大功率附加效率Peak PAE約為23.06 %，整體晶片佈局面積為1.09 mm × 1.16 mm。
第三個電路為具內建線性器之5.3 GHz功率放大器，以第二個電路為基礎，在其輸入端掛接一疊接組態線性器，並透過改變線性器之控制電壓Vctrl而達到控制功率放大器之線性度改善的程度。當功率放大器的Vg1為0.85 V且線性器開啟時，功率增益約14.04 dB，飽和輸出功率Psat約為28.66 dBm，1-dB增益壓縮點之輸出功率OP1dB約為25.11 dBm，最大功率附加效率Peak PAE約為21.00 %，三階交互調變失真IMD3在輸出功率約為19.45 dBm以前皆可抑制在-40 dBc左右，整體晶片佈局面積為1.09 mm × 1.16 mm。

In this paper, three 5.3-GHz power amplifiers are presented, which were separately utilized the technique of transformer power combining, current combining transformer and built-in linearizer, and implemented in TSMC standard 0.18-μm 1P6M CMOS technology. The measurements of three power amplifiers include s-parameters and continuous wave signal.
First, a 5.3 GHz power amplifier with transformer power combining technique has been designed and implemented. To achieve input impedance matching, output power matching and high output power, we utilize the transformer to implement the impedance conversion and the power combining. When the Vg1 of the power amplifier operating in 0.85 V, the power amplifier exhibits the power gain of 18.19 dB, the saturated output power of 26.10 dBm, the output power of 21.20 dBm at 1-dB compression point, the quiescent current of 294.60 mA and the maximum power added efficiency of 21.30 %. The chip size is 1.17 mm × 0.64 mm.
Second, based on the first circuit, a 5.3 GHz power amplifier with current combining transformer technique has been designed and implemented. To achieve the higher output power, current combining transformer technique is adopted. When the Vg1 of the power amplifier operating in 0.85 V, the power amplifier demonstrates the power gain of 16.43 dB, the saturated output power of 29.43 dBm, the output power of 25.44 dBm at 1-dB compression point, the quiescent current of 610.50 mA and the maximum power added efficiency of 23.06 %. The chip size is 1.09 mm × 1.16 mm.
Finally, based on the second circuit, a built-in linearizer utilizing cascode configuration for 5.3 GHz power amplifier has been designed and implemented. The proposed linearization technique which is shunted in the front end of the second circuit aims to control the implement of the linearity of the power amplifier by the Vctrl. After linearization with the Vg1 of the power amplifier operating at 0.85 V, the power amplifier demonstrates the power gain of 14.04 dB, the saturated output power of 28.66 dBm, the output power of 25.11 dBm at 1-dB compression point and the maximum power added efficiency of 21.00 %. Third-order intermodulation distortion can be suppressed below to -40 dBc until the output power of 19.45 dBm. The chip size is 1.09 mm × 1.16 mm.

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