簡易檢索 / 詳目顯示

回結果列表
研究生： 賴宏璟
論文名稱： 具預先偵測動態量化之三角積分調變器設計
The ΔΣ Modulator with Pre-Detective Dynamic Quantization
指導教授： 郭建宏
學位類別： 碩士
Master
系所名稱： 電機工程學系
Department of Electrical Engineering
論文出版年： 2011
畢業學年度： 99
語文別： 中文
論文頁數： 109
中文關鍵詞： 強健型串疊三角積分調變器 、輸入數位前饋 、複數零點帶通三角積分調變器 、動態量化器 、增益強化電流鏡型AB類運算放大器 、時脈平均演算法
英文關鍵詞： SMASH, CIFF, complex zeros bandpass ΔΣ modulator, dynamic quantizer, class AB gain enhanced current mirror OTA, CLA
論文種類： 學術論文
相關次數： 點閱：711  下載：27 
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報

    • 因應現今積體電路設計業的製程技術已邁入奈米科技時代，含有數位與類比電路的低功率混合信號積體電路設計考量也跟著不同。數位電路設計可以有顯著的進步，然而類比電路設計卻被電晶體導通電壓未等比例改進而有所局限。為有效地增加類比數位轉換器精密度並降低耗能於電源供應電壓下降狀況下。本論文介紹兩種類比數位三角積分調變器，分別被推導設計適用於中或低頻區段。首先介紹以學者所提出的強健型串疊三角積分調變器為主體，以減少後端數位濾波器的使用，接著引進數位輸入前饋技術於調變器第一級，將量化誤差傳入第二級後，藉由後端數位減法器的運用，使得所提強健型串疊三角積分調變器使用輸入數位前饋可完整消除第一級的量化誤差。再者提出非純虛數共軛零點落於中心頻率附近，可再次強化輸出解析度。另外搭配部份取樣以及雙取樣技術來降低操作頻率以及各級使用低失真架構，用以減輕電路元件設計負擔。最後，藉由線性軟體模擬架構特性，本論文所提出之六階強健疊接型複數零點帶通三角積分調變器使用延遲數位前饋技術可達訊號雜訊含失真比105.67dB於10.7MHz輸入頻率與200kHz的信號頻寬。另外，本論文亦提出新的多位元量化器的輸出組成表現，藉由偵測器預先判斷訊號走向，接著控制後端動態量化器進行有效的高解析度量化，配合回授補償恢復完整的量化輸出，成功地減少高位元量化器元件過多且複雜的問題。由TSMC 0.18μm 1P6M標準製程製造預計可達訊號雜訊含失真比86.12dB以上。上述三角積分調變器使用本論文所提出之增益強化電流鏡型AB類運算放大器以及時脈平均演算法，並且搭配低供應電壓1.2V來實現。

    In this paper, a sixth-order sturdy multi-stage noise shaping (SMASH) bandpass delta-sigma (ΔΣ) modulator with delaying digital input feedforward structure is presented. The second-order ΔΣ modulator with cascade integrators and distributed feedforward (CIFF) is utilized in each stage to reduce the signal swing. Hence, the requirement of Opamp and the power consumption of circuits can be reduced due to the suppression of the signal swing and the discarding of the digital cancellation filters. One pair of complex zeros is designed within signal bandwidth to effectively suppress the noise floor of the presented modulator. The sub-sampling technique is adopted to reduce the clock frequency and the requirement of Opamp. Simulation results confirm the feasibility of the proposed SMASH CIFF bandpass ΔΣ modulator with delaying DFF structure and the signal-to-noise plus distortion ratio (SNDR) could reach 105.56dB in a 200 kHz of signal bandwidth centered at 10.7 MHz. Besides, another contents presented a dynamic ΔΣ modulator with pre-detective capability. The transmitted signal before quantizing could be detected first. The dynamic quantizer would follow the signal by adjusting different reference voltage during multi-bit quantization. Compare with traditional multi-bit quantization, the number of hardware and complexity would reduce. A super class AB gain enhanced current mirror OTA would also insert in the presented ΔΣ modulator to increase the slew rate in the low voltage operation. The proposed ΔΣ modulator designed by TSMC 0.18μm 1P6M process and consumed 400μW from a 1.2-V supply voltage. The SNDR could reach at least 86.12 dB in a 25 kHz of signal bandwidth centered at 8.9 kHz.

    中文摘要 i 英文摘要 iii 誌謝 v 目錄 vi 表目錄 x 圖目錄 xi 第一章　　緒論 1 1.1 研究動機與背景 1 1.2 論文組成 2 第二章　　三角積分調變器概論 5 2.1 前言 5 2.2 前言 6 2.2.1 解析度 6 2.2.2 信號雜訊比 7 2.2.3 動態範圍 7 2.3 量化器 8 2.3.1 一位元量化器 8 2.3.2 多位元量化器 9 2.3.2.1 Mid-rise多位元量化器 10 2.3.2.2 Mid-tread多位元量化器 10 2.3.3 多位元量化器的非理想效應 11 2.3.4 量化誤差 12 2.3.5 量化雜訊的線性模型 13 2.4 取樣定理 14 2.5 超取樣技術 15 2.6 雜訊移頻的三角積分調變器 16 2.6.1 一階雜訊移頻的三角積分調變器 17 2.6.2 二階雜訊移頻的三角積分調變器 21 2.6.2.1 傳統型二階三角積分調變器 21 2.6.2.2 低失真型二階三角積分調變器 23 2.6.2.3 低失真型與傳統型二階三角積分調變器比較 24 2.6.3 高階雜訊移頻 25 2.6.3.1 單迴路架構 27 2.6.3.2 串疊架構 29 2.6.4 帶通三角積分調變器 30 2.6.4.1 超外差式接收器 30 2.6.4.2 單一中頻式接收器 31 2.7 總結 32 第三章　　三角積分調變器的電路元件 33 3.1 前言 33 3.1 開關電容式電路 33 3.1.1 非反相積分器 33 3.1.2 反相積分器 35 3.2 開關 36 3.2.1 低臨界電壓製程 37 3.2.2 電壓增強技術 37 3.2.3 靴帶型開關 39 3.2.4 使用靴帶型開關為取樣電路 39 3.3 增益強化電流鏡型AB類運算放大器 41 3.3.1 AB類輸入對作原理 43 3.3.2 共模回授電路 47 3.3.3 偏壓電路 48 3.4 多位元量化器 48 3.4.1 比較器 51 3.5 動態元件不匹配 51 3.5.1 資料權重平均法 52 3.5.2 時脈平均演算法 52 3.6 非重疊時脈產生器 53 3.7 總結 54 第四章　　六階強健疊接型複數零點帶通三角積分調變器使用延遲數位前饋技術 55 4.1 前言 55 4.2 電路架構 55 4.2.1 類比前饋型低失真架構 56 4.2.2 數位前饋型低失真架構 56 4.2.3 強健型串疊三角積分調變器 57 4.2.4 強健型串疊三角積分調變器使用輸入數位前饋 58 4.2.4.1 強健型串疊三角積分調變器使用輸入延遲數位前饋 59 第五章　　具預先偵測特性之動態三角積分調變器 71 5.1 前言 71 5.2 設計想法 72 5.2.1 改變量化輸出組成 73 5.2.2 動態量化器操作步驟與三角積分調變器線性模型建立 74 5.2.3 三角積分調變器之非理想效應 78 5.2.3.1 熱雜訊 78 5.2.3.2 取樣電容值 78 5.2.3.3 運算放大器有限增益 80 5.2.3.4 時脈抖動 81 5.2.3.5 調變器線性系統架構包含非理想效應 82 5. 3 預先偵測功能之動態三角積分調變器電路實現 84 5.3.1 三角積分調變器電路系統模擬 93 5.3.2 三角積分調變器電路系統電路佈局與晶片腳位配置圖 94 5. 4 實驗環境建構 97 5.4.1 輸入訊號與輸入界面電路 98 5.4.2 供應電壓 98 5.4.3 參考電壓 99 5.4.4 參考電壓腳位端的濾波槽電路 100 5.5 預計實驗結果以及結論 100 第六章　　總結與未來展望 101 6.1 總結 101 6.2 未來展望 103 參考文獻 105

    [1] E. E. Fabris, L. Carro, S. Bampi, “A Digitally Rceonfigurable Sensor Interface for SOC Using Delta-Sigma Modulators,”IEEE Conf. Instrumentation and Measurement Technology, Sorrento, Italy, Apr. 2006.
    [2] K. Noguchi, T. Hashida, M. Nagata, “On-Chip Analog Circuit Diagnosis in Systems-on-Chip Integration,”IEEE Proc. European Solid-State Circuits, ESSCIRC, Sept. 2006.
    [3] D. A. Johns, K. Martin, “Analog Integrated Circuit Design,”John Wiley & Sons, Inc. 2006.
    [4] J. Silva, U. K. Moon, J. Steensgard, and G, C. Temes, “Wideband Low-Distortion Delta-Sigma ADC Topology,”Electronic. Lett., vol. 37, pp.737-738, Jun. 2001.
    [5] S. R. Norsworthy, R. Schreier, and G, C. Temes, Delta-Sigma Data Converters: Throry, Design, and Simulation, IEEE Pree, New Tork, 1997.
    [6] R. Schreier, and G, C. Temes, Understanding Delta-Sigma Data Converters, IEEE Pree, Wiley & Sons, 2005.
    [7] K. C. H. Chao, S. Nadeem, W. L. Lee, and C. G. Sodini,“A Higher-Order Topology for Interpolative Modulators for Oversampling A/D Converters,”IEEE Trans. on Circuits and Systems, vol. 37, pp.309-318, Mar.1990.
    [8] W. L. Lee, and C. G. Sodini,“A Topology for Higher-Order Coders,”in Proc. of IEEE Symp. on Circuits and Systems, pp.459-462, 1987.
    [9] B. Delsignore, D. Kerth, N. Sooch, and E. Swansoon, “A Monolithic 20-B Delta-Sigma Modulator,”IEEE J. Solid-State Circuits, vol. SC-29, pp.1311-1317.
    [10] T. Ritoniemi, T. Karema, and H. Tenhunen,“The Design of Stable High Order 1-Bit Sigma-Delta Modulator”in Proc. IEEE Symp. CAS, pp. 3267-3270, May.1990.
    [11] P. Ferguson, Jr., et al., “An 18b 20kHz Dual Sigma-Delta A/D Converter” IEEE J. Solid-State Circuits, Feb. 1991.
    [12] A. Hairapetian, “An 81-Mhz IF Receiver in CMMOS,” IEEE J. Solid-State Circuits, vol. 31, no. 12, 1996.
    [13] A. Jantzi, K. Martin, M. Snelgrove, and A. Sedra, “A Complex Bandpass Delta-Sigma Converter for Digital Radio,”in Proc. IEEE ISCAS, 1994, pp. 453-456.
    [14] A. Swaminathan, “A Single-IF Receiver Architecture Using a Complex Sigma-Delta Modulator,”these for the degree of Master, Ottwa-Carleton Institute Department of Electronics Faculty of Engineering, Carleton Univerity, Ottawa, Canada.
    [15] R. T. Baird and T. S. Fiez, “Linaerity Enhancement if Multibit ΔΣ A/D and D/A Converters using Data Weighted Averaging,”IEEE Trans. Circuits Syst. II, vol. 42, pp. 753-762, Dec. 1995.
    [16] T. Tille, J. Sauerbrey, and D. Schmitt-Landsidel, “A Low Voltage MOSFET-Only ΣΔ Modulator for Speech Band Applications Using Depletion-Mode MOS-Capacitors in Combined Series and Parallel Compensation,” in Proc. IEEE ISCAS, vol. 1,no. 3, May 2001, pp. 376-379.
    [17] J. Sauerbrey, T. Tille, D. S. Landsidel, and R. Thewes, “A 0.7-V MOSFET-Only Switched-Opamp ΔΣ Modulator in Standard Digital CMOS Technology,”IEEE J. Solid-State Circuits, vol. 37, no. 12, Dec. 2002.
    [18] M. Steyaert, J. Crols, and S. Gogaert, “Switched-Opamp:a Technique for Realizing Full CMOS Switched-Capacitor Filters at very Low-Voltages,” in Proc. ESSCIRC, pp. 178-181, Sep. 1993.
    [19] G. Ahn, D. Chang, M. Brown, N. Ozaki, H. Youra, K. Hamashita, K. Takasuka, G. Temes, and U. K. Moon, “0.6-V 82-dB Delta-Sigma Audio ADC using Switched-RC Integrators,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2398-2461, Dec. 2005.
    [20] M. Keskin, “A Low-Voltage CMOS Switch with A Novel Clock Boosting Scheme,” IEEE Trans. Circuits Syst. II, vol. 52, pp. 185-188, Apr. 2005.
    [21] M. G. Kim, G. C. Ahn, P. K. Hanumolu, S. H. Lee, S. H. Kim, S. B. You, J. W. Kim, G. C. Temes and U. K. Moon, “A 0.9V 92dB Double-Sampled Switched-RC Delta-Sigma Audio ADC,” IEEE J. Solid-State Circuits, vol. 43, pp. 1195-1206, May. 2008.
    [22] J. B. da Silva, “High-Performance Delta-Sigma Analog-to-Digital Converters,” Phd Thesis, Oregon State University, July. 2004.
    [23] S. Au and B. H. Leung, “A 1.95V 0.4mW 12-b Sigma-Delta Modulator Stabilized by Local Feedback Loops,” IEEE J. Solid-State Circuits, vol. 32, no. 3, pp. 321-328, Mar. 1997.
    [24] S. Baswa, A. Lopez-Martin, J. Ramirez-Angulo, and R. G. Carvajal,. “Low-Voltage Super Class-AB CMOS OTA,” Electron. Lett., vol. 40, no. 4, pp. 216-217, Feb. 2004.
    [25] A. Lopez-Martin, S. Baswa, J. Ramirez-Angulo, and R. G. Carvajal,. “Low-Voltage Super Class-AB CMOS OTA Cell with Very High Slew Rate and Power Efficiency,” IEEE J. Solid-State Circuits, vol. 40, no. 5, pp. 1068-1077, May. 2005.
    [26] J. A. Galan, A. Lopez-Martin, R. G. Carvajal,. J. Ramirez-Angulo, and C. Rubia-Marcos, “Super Class-AB CMOS OTA With Adaptive Biasing and Dynamic Output Current Scaling,” IEEE Trans. Circuits Syst.I, vol. 54, no. 3, pp. 449-457, March. 2007.
    [27] V. Peluso, P. Vancorenland, A. M. Marques, M. Steyaert, and W. Sansen,. “A 900-mW Low-Power ΣΔ A/D Converter with 77-dB Dynamic Range ,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1887-1897, Dec. 1998.
    [28] L. Yao, M. Steyaert, and W. Sansen, “A 0.8-V, 8-μW CMOS OTA with50-dB gain and 1.2-MHz GBW in 18-pF load,” IEEE J. Solid-State Circuits, pp. 297–300, Sept. 2003.
    [29] L. Yao, M. Steyaert, and W. Sansen, “A 1-V 140-μW 88-dB Audio Sigma-Delta Modulator in 90-nm CMOS,” IEEE J. Solid-State Circuits. vol. 39, no. 11, Nov. 2004.
    [30] M. J. Story, “Digital to Analogue Converter Adapted to Select Input Sources Based on a Preselected Algorithm Once Per Cycle of a Sampling Signal,” U. S. patent number 5138317, Aug. 1992.
    [31] R.T. Baird and T. S. Frez, “Improved ΔΣ DAC Linearity Using Data Weighted Averaging,”in Proc. of IEEE Symp. on Circuits and Systems, vol.1 pp.13-16, May. 1995
    [32] L. R. Carley. “A Noise-Shaping Coder Topology for 15+ Bit Converters,” IEEE J. Solid-State Circuits. vol. 24, no. 2, April. 1989.
    [33] A. A. Hamoui, M. Sukhon, and F. Maloberti, “Digitally-Enhanced 2nd-OrderΔΣModulator with Unity-Gain Signal Transfer Function,” in Proc. IEEE Int. Symp. Circuits Syst., pp.1664 - 1667 , 2008.
    [34] A. A. Hamoui, M. Sukhon, and F. Maloberti, “Digitally-enhanced high-order ΔΣ modulators,” in Proc. IEEE Int. Conf. Electron. Circuits Syst., 2008, pp.1115-1118.
    [35] A. Gharbiya, and D. A. Johns, “On the implementation of input feedforward delta-sigma modulators,” IEEE Trans. Circuits Syst. I, vol. 53, no. 6, pp. 453-457, 2006.
    [36] P. Benabes, A. Gauthier, and R. Kielbasa, “New high-order universal delta-sigma modulators,” Electron. Lett., 5th, vol. 31, no. 1, pp. 8-9, Jan. 1995.
    [37] A. Morgado, R. del Río, and J.M. de la Rosa, “A new cascade sigma-delta modulator for low-voltage wideband applications,” Electron. Lett., 16th, vol. 43, no. 17, pp. 8-9, Aug. 2007.
    [38] N. Maghari, S. Kwon, G.C. Temes, and U. Moon, “Sturdy MASH ΔΣ modulator,” Electron. Lett., vol. 42, pp.1269-1270, Oct. 2006.
    [39] N. Maghari, S. Kwon, G. C. Temes, and U. Moon, “Mixed-order sturdy MASH ΔΣ modulator,” in Proc. IEEE Int. Symp. Circuits Syst., 2007, pp. 257-260.
    [40] X. Lu, “A novel signal-predicting multibit delta-sigma modulator,” in Proc. of the IEEE Intl. Conf. on Electronics, Circuits and Sys., Dec 2004, pp.105 -108.
    [41] L. Dorrer, F. Kuttner, P. Greco, P. Torta, and T. Hartig, “A 3-mW 74-dBSNR 2-MHz continuous-time Delta-Sigma ADC with a tracking ADC quantizer in 0.13-um CMOS,” vol. Vol.40, pp. 2416 – 2426, Dec. 2005.
    [42] S. Pesenti, P. Clement and M. Kayal , “Reducing the Number of Comparators in Multi-Bit ΔΣ Modulators,” IEEE Trans. Circuits Syst.I, vol. 55, no. 4, pp. 1011-1022, May. 2008.
    [43] K. P. Pun, S. Chatterjee, and P. R. Kinget, “A 0.5-V 74-dB SNDR 25-kHz Continuous-Time Delta-Sigma Modulator with a Return-To-Open DAC,” IEEE J. Solid-State Circuits, vol. 42, no. 3, pp.496-507, Mar. 2007.
    [44] J. Sauerbrey, T. Tille, D. S. Landsiedel, and R. Thewes, “A 0.7-V MOSFET-Only Switches-Opamp ΔΣ Modulator In Standard Digital CMOS Technology,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp.1662–1669, Dec. 2002.
    [45] L. Yao, M. S. J. Steyaert, and W. Sansen, “A 1-V 140-μW 88-dB Audio Sigma–Delta Modulator in 90-nm CMOS,” IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 1809–1818, Nov. 2004.
    [46] G. Ahn, D. Chang, M. Brown, N. Ozaki, H. Youra, K. Hamashita, K. Takasuka, G. Temes, and U. K. Moon, “0.6-V 82-dB Delta–Sigma Audio ADC Using Switched-RC Integrators,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2398–2407, Dec. 2005.
    [47] J. Goes, B. Vaz, R. Monteiro, and N. Paulino, “A 0.9 V ΔΣ Modulator with 80 dB SNDR and 83 dB DR Using A Single-Phase Technique,” in Proc. ISSCC, Feb. 2006, pp. 74–75.
    [48] Y. Chae, I. Lee, and G. Han, “A 0.7V 36μW 85dB-DR Audio ΔΣ Modulator Using Class-C Inverter,” in Proc. ISSCC, Feb. 2008, pp. 490–491.
    [49] J. Ron, S. Byun, Y. Choi, H. Roh, Y. G. Kim, and J. K. Kwon, “A 0.9-V 60-μW 1-Bit Fourth-Order Delta–Sigma Modulator with 83-dB Dynamic Range,” IEEE J. Solid-State Circuits, vol. 43, no. 2, pp. 361–370, Feb. 2008.
    [50] J. Wang, T. Matsuoka, and K. Taniguchi, “A 0.5 V Feedforward Delta–Sigma Modulator with Inverter-Based Integrator,” in Proc. ESSCIRC, 2009, pp. 328–331.

    下載圖示
    QR CODE