由於科技快速的發展下，3C產品為了滿足更高的效能與更低的功耗，使得同面積下晶片內電晶體的密度必須不斷的翻倍，為了克服其無法避免的漏電流問題，電晶體架構從最初的平面式電晶體發展演變成了立體結構的鰭式電晶體FinFET再到最近幾年相當火熱的環繞式閘極電晶體GAAFET，進而使閘極能夠有效的控制通道。此外，由於鐵電材料的發現與突破應用於記憶體領域方面有極大的潛力，因此同樣獲得大量的關注與研究，而鐵電材料與CMOS製程優良的適應性與兼容性被視為未來可取代傳統NAND的明日之星。 此論文分成幾個部分，第一部分首先會先討論電晶體的演變以及方向，接著說明鐵電材料的發現以及應用。第二部分接著探討MFM鐵電電容過程中使用了TSRI的I-Line 365 nm曝光機、乾濕蝕刻、CVD化學氣象沉積、PVD物理氣象沉積與關鍵的ALD原子層沉積系統等等，重要部分有像是調整ALD中鋯(Zr)以及鉿(Hf)元素前驅物的比例及順序來開發出所謂的固溶體(Solid-Solution)結構以及超晶格(Superlattice)結構來與3D電晶體元件做搭配，其中反鐵電的特性使得耐久性(Endurance)與操作速度大幅提高，有望未來能夠在記憶體產業占有一席之地。第三部分為將鐵電材料應用於GAA的部分，本章節會詳細介紹如何使用SOI晶圓經過不同製程直到做出元件並且配合場發射穿透式電子顯微鏡(TEM)來對元件進行分析，其中重要的部分像是選擇曝光條件以及如何大幅使矽通道進行減薄也會在此章節詳細說明。第四部分為FTJ -Vertical電晶體之製程，使用搭配了超晶格(Superlattice) 之鐵電結構並且顯現了在小尺寸下依舊能夠展示出優異的鐵電特性以及相當適合應用於3D NAND 之架構。

Due to the rapid development of technology, 3C products have continuously doubled the density of transistors on the same area in order to meet higher performance and lower power consumption requirements. To overcome the inevitable physical limitations, transistor structures have evolved from planar transistors to three-dimensional FinFETs and the recently popular Gate-All-Around Field-Effect Transistors (GAAFETs). All of these advancements aim to address the increasing leakage current issue caused by size scaling and enable effective control of the channel by the gate. Additionally, the discovery and breakthrough of ferroelectric materials have shown great potential in the field of memory, receiving significant attention and research. The excellent adaptability and compatibility of ferroelectric materials with CMOS processes make them a promising candidate to replace traditional NAND in the future.
This paper is divided into several parts. In the first part, the evolution and direction of transistors will be discussed, followed by an explanation of the discovery and applications of ferroelectric materials. The second part focuses on the MIM ferroelectric capacitor process, which involves the use of equipment such as TSRI's I-Line 365 nm exposure machine, dry/wet etching, CVD chemical vapor deposition, PVD physical vapor deposition, and the key ALD atomic layer deposition system at the Nanotechnology Center of National Taiwan University. Important aspects include the adjustment of the proportions and sequence of Zr and Hf precursor materials in ALD to develop nano-laminated and superlattice structures, which are then combined with 3D transistor devices to demonstrate different characteristics. The anti-ferroelectric properties significantly enhance endurance and operational speed, potentially securing a position in the memory industry.
The third part focuses on the application of ferroelectric materials in Gate-All-Around (GAA) transistors. This chapter provides a detailed introduction to the process flow from the initial SOI wafer to the final device, including analysis using transmission electron microscopy (TEM). Important aspects such as exposure conditions, parameters selection, and thinning of the silicon channel in GAA are thoroughly explained. The fourth part discusses the process of FTJ (Ferroelectric Tunnel Junction) -Vertical transistors. By utilizing ferroelectric structures with superlattices, these transistors demonstrate excellent ferroelectric characteristics even at small sizes, making them highly suitable for 3D NAND architectures.

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