延遲鎖定迴路因為為一階恆穩定回授系統面積小好設計外，還有雜訊在電壓控制延遲嚴上不會累積雜訊，輸出時脈抖動小的優點，被用來當成時脈產生器的使用上如:記憶體介面、液晶顯示器、無線電傳輸系統...等，成為近幾年來受歡迎的電路架構。然而，改善鎖定時間長和因為雜訊產生的非理想抖動是設計延遲鎖定迴路重要的課題，本文分別針對此問題，提出改善方法。
本延遲所定迴路，利用電壓控制延遲線一個週期延遲時間固定的特性，設計一個時脈頻率預測器，在延遲所定迴路的迴授系統運作之前，改變初始電壓到接近鎖定電壓的位準，再進行延遲所定迴路的迴授系統運作，利用充電幫浦的校正到鎖定電壓，縮短所定時間，使得電路能有快速鎖定的功能。除此之外，為了降低輸出時脈的抖動，本延遲鎖定迴路使用自動抖動校正電路產生一個延遲與兩個相位偵測器組合成一個假相位偵測器，縮小系統的抖動區域，得到較低的輸出時脈抖動。
本延遲鎖定迴路採用CMOS 0.18um 1P6M 標準製程，核心面積為0.77x0.84mm2，功率消耗為29mW操作在400MHz，可鎖範圍為150MHz~550MHz，鎖定時間為低於9cycles，peak-to-peak jitter為2.9ps操作在400MHz。

With a first order system and the noise would not accumulate in the voltage controlled delay line (VCDL), delay-locked loop has advamtages such as: easy to design, having small aarea and good jitter performance for clock generator.So it is becoming a popular architecture used in memory intergface, LCD, wireless communication system... etc. However, the locking time and the jitter caused by non-ideal effect are important topics for delaylocked loop. In this paper, we proposed an auto jitter calibration delay-locked loop with fast locking feature to overcome these two problems.
The proposed delay-locked loop, causing the voltage controlled delay line, VCDL's "A fixed latency of one clock cycle,"[9], we design a frequency estimator circuit to change the initial voltage at the almost locking level to accelerate the locking time before the DLL's feedback system of charge pump's fine tuning until the DLL is locked. In addition, the proposed DLL using an auto jitter calibration to produce a little delay that is combining two phase frequency detectors to suppress the jitter area, and the output jitter is smaller.
The proposed DLL is fabricated in CMOS 0.18μm 1P6M technology. The core area is 0.77x0.84mm2 and the power dissipation is 29m at 400MHz. The locking range is 150MHz~550MHz and the locking time is <9 cycles. The Peak-to-Peak Jitter is 2.9ps at 400MHz.

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