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研究生： 趙祐
Chao, Yu
論文名稱： 具 1-1 MASH 架構的雜訊移頻循序漸進式類比數位轉換器設計與實現
Design and Implementation of a Noise-Shaping SAR ADC with 1-1 MASH Structure
指導教授： 郭建宏
Kuo, Chien-Hung
口試委員： 黃育賢
Hwang, Yuh-Shyan
陳建中
Chen, Jiann-Jong
郭建宏
Kuo, Chien-Hung
口試日期： 2023/01/10
學位類別： 碩士
Master
系所名稱： 電機工程學系
Department of Electrical Engineering
論文出版年： 2023
畢業學年度： 111
語文別： 中文
論文頁數： 103
中文關鍵詞： 類比數位轉換器 、三角積分調變器 、循序漸進式類比數位轉換器 、雜訊移頻循序漸進式類比數位轉換器 、多級雜訊移頻 、基於反向器轉導放大器 、無加法器求和電路
英文關鍵詞： Analog-to-Digital Converter, Delta-Sigma Modulator, successive approximation register ADC, Noise-Shaping SAR ADC, Multistage Noise-Shaping, Inverter-Based OTA, Adder-Free Summing Circuit
DOI URL： http://doi.org/10.6345/NTNU202300407
論文種類： 學術論文
相關次數： 點閱：108  下載：21 
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    • 本文提出一種具1-1多級雜訊移頻(Multistage Noise-Shaping, MASH)架構的雜訊移頻循序漸進式(Noise-Shaping Successive-Approximation Register, NS-SAR)類比數位轉換器(Analog-to-Digital Converter, ADC)。所提出的類比數位轉換器是一種混合型超取樣(Oversampling)類比數位轉換器結構，它結合了循序漸進式與三角積分(Delta-Sigma, ΔΣ)兩種類比數位轉換器的優點，可以在實現高解析度及大頻寬的同時並具有良好功耗效率。此三角積分調變器設計中的單級迴路使用具前饋求和的級聯積分器(Cascade of Integrators with Feed-Forward Summation, CIFF)架構，由於CIFF架構中積分器的路徑上不包含輸入訊號，迴路濾波器僅需處理調變過程中產生的量化誤差，因此迴路濾波器的輸出振幅很小，意味著可以放寬轉導放大器(Operational Transconductance Amplifier, OTA)設計上的迴轉率性能要求，也代表該架構的迴路濾波器適合用架構簡單且功耗低的基於反向器的轉導放大器來實現。此外，為了降低電路的複雜度，作者提出了一種無加法器的求和電路結構，它在不依賴額外電路的情況下實現了CIFF架構的輸入前饋求和功能和提取MASH架構的第一級量化誤差。
    所提出的電路使用TSMC 0.18-μm 1P6M標準CMOS製程技術所製造。不含PAD的晶片核心面積為0.084 mm2。在供應電壓1.4 V、取樣頻率4.0-MS/s、20 kHz及的頻寬下，實現了72.9 dB的訊號雜訊失真比(Signal-to-Noise and Distortion Ratio, SNDR)。此外，端看功率頻譜密度圖的斜率驗證了具有完整的二階雜訊移頻。

    This thesis presents a noise-shaping successive approximation register (NS-SAR) analog-to-digital converter (ADC) with 1-1 multistage noise-shaping (MASH) structure. The proposed ADC is a hybrid oversampling ADC architecture that combines the advantages of both SAR and delta-sigma (ΔΣ) ADCs and can achieve high resolution and wide bandwidth with good power efficiency. The single stage topology in the ΔΣM design using cascade of integrators with feed-forward summation (CIFF) structure. Because the output signals of integrators in CIFF structure are not contain the input signal, which means that this loop filter process quantization error only, thus the output swing requirements of the loop filter will decrease, it means that the slew-rate requirement is not critical when we design the operational transconductance amplifier (OTA) in loop filter, so it is more suitable for inverter-based OTA. Besides, the author proposed an adder-free summing circuit architecture to reduce circuit complexity, which realizes the input feed-forward summing function of the CIFF structure and extracts the 1st quantization error of the MASH structure without relying on additional circuits.
    The prototype was fabricated using TSMC 0.18-μm 1P6M CMOS technology. The chip core area without PADs is 0.084 mm2. At 1.4 V supply, sampling rate of 4.0-MS/s, bandwidth of 20 kHz, the prototype achieves 72.9 dB SNDR. Besides, the slope of power spectral density (PSD) verifies the almost 2nd noise-shaping successfully.

    第一章 緒論 1 1.1 研究背景與動機 1 1.2 積體電路設計流程 2 1.3 論文架構與概要 4 第二章 類比數位轉換器概論 5 2.1 基本原理 5 2.2 量化器與量化誤差 7 2.2.1 單位元量化器 7 2.2.2 多位元量化器 8 2.2.3 量化誤差 9 2.3 靜態參數 11 2.3.1 增益誤差 11 2.3.2 偏移誤差 12 2.3.3 微分非線性 12 2.3.4 積分非線性 13 2.3.5 遺失碼 14 2.4 動態參數 15 2.4.1 訊號雜訊比 15 2.4.2 訊號雜訊失真比 16 2.4.3 有效位元數 16 2.4.4 動態範圍 17 2.4.5 無雜散訊號動態範圍 17 2.4.6 總斜波失真 18 2.4.7 總斜波失真加雜訊 18 2.4.8 品質因數 18 2.5 類比數位轉換器類型及應用 20 2.6 雜訊移頻三角積分調變器 21 2.6.1 超取樣 21 2.6.2 雜訊移頻 23 2.6.3 一階雜訊移頻 25 2.6.4 多接雜訊移頻 28 2.6.5 雜訊移頻架構種類 32 2.6.6 閉迴路系統架構種類 35 2.7 循序漸進式類比數位轉換器 38 2.7.1 二分搜尋演算法 38 2.7.2 電路工作流程 39 2.8 快閃式類比數位轉換器 40 第三章 類比數位轉換器之基本電路元件 41 3.1 基本電路元件應用 41 3.2 開關電路 41 3.2.1 MOS開關 41 3.2.2 傳輸閘互補式開關 43 3.2.3 靴帶式開關 43 3.3 取樣保持電路 45 3.4 基於反向器之轉導放大器 46 3.5 動態比較器 48 3.6 切換電容式積分器 49 3.6.1 反向積分器 49 3.6.2 非反向積分器 50 3.7 正反器 52 3.7.1 D型正反器 52 3.7.2 真單相位時脈正反器 53 3.8 循序漸進式暫存器 55 3.8.1 移位暫存器 55 3.8.2 數位類比轉換暫存器 56 3.9 二進制標度數位類比轉換器 56 3.9.1 二進制權重電阻數位類比轉換器 56 3.9.2 二進制權重電流模式數位類比轉換器 57 3.9.3 二進制權重電荷重新分配數位類比轉換器 58 3.10 溫度計編碼數位類比轉換器 59 3.10.1 溫度計編碼電阻數位類比轉換器 60 3.10.2 溫度計編碼電流模式數位類比轉換器 60 3.10.3 溫度計編碼電荷重新分配數位類比轉換器 61 3.11 時脈產生器 62 3.11.1 除頻器 62 3.11.2 非重疊時脈電路 63 3.12 佈局電容 64 3.12.1 金屬氧化物半導體電容 64 3.12.2 金屬絕緣層金屬電容 64 3.12.3 金屬氧化層金屬電容 65 第四章 1-1 MASH架構雜訊移頻循序漸進式類比數位轉換器 67 4.1 雜訊移頻循序漸進式類比數位轉換器概念 67 4.2 三角積分調變器架構考量 68 4.2.1 1-1前饋式多級雜訊移頻架構 68 4.2.2 Matlab & Simulink模擬線性模型 69 4.3 電路架構 71 4.3.1 循序漸進式量化器實現 72 4.3.2 比較器非同步時脈實現 73 4.3.3 無加法器求和電路實現 74 4.3.4 傳輸閘同步時脈實現 76 4.3.5 時脈產生器實現 76 4.4 電路非理想效應 77 4.4.1 熱雜訊 77 4.4.2 時脈抖動 78 4.4.3 放大器有限增益 80 4.4.4 循序漸進式量化器迴授損耗 81 4.5 電路實現 82 4.5.1 電路設計與模擬 82 4.5.2 電路佈局與模擬 85 第五章 研究成果與未來展望 91 5.1 晶片量測設備、量測環境及量測結果 91 5.1.1 晶片量測印刷電路板建立 91 5.1.2 晶片量測環境建立 95 5.1.3 晶片量測結果 96 5.1.4 總結 97 5.2 未來展望 98 參考文獻 99 自傳 103 學術成就 103

    T. C. Carusone, D. A. Johns and K. W. Martin, Analog Integrated Circuit Design, 2nd Edition. John Wiley & Sons, Inc. 2011.
    P. E. Allen and D. R. Hollberg, CMOS Analog Circuit Design, 3rd Edition. Oxford University Press, Inc. 2012.
    B. Razavi, Design of Analog CMOS Integrated Circuits. 2nd Edition. McGraw-Hill Education, Inc. 2017.
    S. Pavan, R. Schreier and G. C. Temes, Understanding Delta-Sigma Data Converters. 2nd Edition, John Wiley & Sons, Inc. 2017.
    D. Marolt, J. Scheible and G. Jerke, “A Practical Layout Module Pcell Concept for Analog IC Design,” in Proc. CDNLive! EMEA, May 2013, pp. 1-10.
    H. Y. Tai, Y. S. Hu, H. W. Chen and H. S. Chen, “A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS,” in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2014, pp. 196-197.
    X. Tang, L. Chen, J. Song and N. Sun, “A 1.5fJ/conv-step 10b 100kS/s SAR ADC with gain-boosted dynamic comparator,” in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC), Nov. 2017, pp. 229-232.
    S. E. Hsieh and C. C. Hsieh, “A 0.44-fJ/Conversion-Step 11-Bit 600-kS/s SAR ADC With Semi-Resting DAC,” IEEE J. Solid-State Circuits, vol. 53, no. 9, pp. 2595-2603, Sep. 2018.
    J. A. Fredenburg and M. P. Flynn, “A 90-MS/s 11-MHz-Bandwidth 62-dB SNDR Noise-Shaping SAR ADC,” IEEE J. Solid-State Circuits, vol. 47, no. 12, pp. 2898-2904, Dec. 2012.
    Z. Chen, M. Miyahara and A. Matsuzawa, “A 2nd order fully-passive noise-shaping SAR ADC with embedded passive gain,” in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC), Nov. 2016, pp. 309-312.
    H. Zhuang et al., “A Second-Order Noise-Shaping SAR ADC With Passive Integrator and Tri-Level Voting,” IEEE J. Solid-State Circuits, vol. 54, no. 6, pp. 1636-1647, Jun. 2019.
    L. Jie, B. Zheng and M. P. Flynn, “A Calibration-Free Time-Interleaved Fourth-Order Noise-Shaping SAR ADC,” IEEE J. Solid-State Circuits, vol. 54, no. 12, pp. 3386-3395, Dec. 2019.
    N. Maghari, S. Kwon, G. C. Temes and U. Moon, “Mixed-Order Sturdy MASH Δ-Σ Modulator,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), 2007, pp. 257-260.
    A. Suadet and V. Kasemsuwan, “A CMOS inverter-based class-AB pseudo differential amplifier for HF applications,” 2010 in Proc. IEEE Int. Conf. Electron Devices and Solid-State Circuits (EDSSC), 2010, pp. 1-4.
    P. Wang, G. Csaba, W. Porod and T. Ytterdal, “A differential inverter-based switched-capacitor oscillator in 65 nm CMOS technology,” European Conf. on Circuit Theory and Design (ECCTD), Trondheim, Norway, 2015, pp. 1-4.
    B. Razavi, “The Bootstrapped Switch [A Circuit for All Seasons],” IEEE Solid-State Circuits Magazine, vol. 7, no. 3, pp. 12-15, Summer 2015.
    B. Razavi, “TSPC Logic [A Circuit for All Seasons],” IEEE Solid-State Circuits Magazine, vol. 8, no. 4, pp. 10-13, Fall 2016.
    R. H. Walden, “Analog-to-digital converter survey and analysis,” IEEE J. Selected Areas in Comm., vol. 17, no. 4, pp. 539-550. Apr. 1999.
    R. Zanbaghi, S. Saxena, G. C. Temes and T. S. Fiez, “A 75-dB SNDR, 5-MHz Bandwidth Stage-Shared 2–2 MASH ΔΣ Modulator Dissipating 16 mW Power,” IEEE Trans. Circuits and Syst. I, Reg. Papers, vol. 59, no. 8, pp. 1614-1625, Aug. 2012.
    J. Liu, S. Li, W. Guo, G. Wen and N. Sun, “A 0.029-mm2 17-fJ/Conversion-Step Third-Order CT ΔΣ ADC With a Single OTA and Second-Order Noise-Shaping SAR Quantizer,” IEEE J. Solid-State Circuits, vol. 54, no. 2, pp. 428-440, Feb. 2019. 
    P. Bisiaux, C. Lelandais-Perrault, A. Kolar, P. Benabes and F. Vinci dos Santos, "A 14-b two-step inverter-based ΣΔ ADC for CMOS image sensor," in Proc. IEEE Int. New Circuits and Syst. Conf. (NEWCAS), 2017, pp. 217-220.
    C. -C. Liu, S. -J. Chang, G. -Y. Huang and Y. -Z. Lin, “A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 731-740, Apr. 2010.
    N. -C. Chen, P. -Y. Chou, H. Graeb and M. P. -H. Lin, “High-density MOM capacitor array with novel mortise-tenon structure for low-power SAR ADC,” Design, Automation & Test in Europe Conf. & Exhibition (DATE), Lausanne, Switzerland, 2017, pp. 1757-1762.
    F. Michel and M. S. J. Steyaert, “A 250 mV 7.5 μW 61 dB SNDR SC ΔΣ Modulator Using Near-Threshold-Voltage-Biased Inverter Amplifiers in 130 nm CMOS,” IEEE J. Solid-State Circuits, vol. 47, no. 3, pp. 709-721, Mar. 2012.
    Y. Yoon, H. Roh and J. Roh, “A True 0.4-V Delta–Sigma Modulator Using a Mixed DDA Integrator Without Clock Boosted Switches,” IEEE Trans. Circuits and Syst. II, Exp. Briefs, vol. 61, no. 4, pp. 229-233, Apr. 2014.
    J. -E. Park, Y. -H. Hwang and D. -K. Jeong, “A 0.4-to-1 V Voltage Scalable ΔΣ ADC With Two-Step Hybrid Integrator for IoT Sensor Applications in 65-nm LP CMOS,” IEEE Trans. Circuits and Syst. II, Exp. Briefs, vol. 64, no. 12, pp. 1417-1421, Dec. 2017.
    P. C. C. de Aguirre and A. A. Susin, “A 0.6-V, 74.2-dB DR Continuous-Time Sigma–Delta Modulator With Inverter-Based Amplifiers,” IEEE Trans. Circuits and Syst. II, Exp. Briefs, vol. 65, no. 10, pp. 1310-1314, Oct. 2018.
    J. Warchall, S. Kaleru, N. Jayapalan, B. Nayak, H. Garudadri and P. P. Mercier, “A 678-μW Frequency-Modulation-Based ADC With 104-dB Dynamic Range in 44-kHz Bandwidth,” IEEE Trans. Circuits and Syst. II, Exp. Briefs, vol. 65, no. 10, pp. 1370-1374, Oct. 2018. 
    L. Lv, X. Zhou, Z. Qiao and Q. Li, “Inverter-Based Subthreshold Amplifier Techniques and Their Application in 0.3-V ΔΣ-Modulators,” IEEE J. Solid-State Circuits, vol. 54, no. 5, pp. 1436-1445, May 2019.
    H. Liu et al., “A Hybrid 1st/2nd-Order VCO-Based CTDSM With Rail-to-Rail Artifact Tolerance for Bidirectional Neural Interface,” IEEE Trans. Circuits and Syst. II, Exp. Briefs, vol. 69, no. 6, pp. 2682-2686, June 2022.
    S. Rabii and B. A. Wooley, The Design of Low-Voltage, Low-Power Sigma Delta Modulator, Kluwer academic publisher, 1999.
    TSMC Logic Technology (https://www.tsmc.com/english/dedicatedFoundry/technology/logic)
    DS360低失真波形產生器(https://www.thinksrs.com/downloads/pdfs/catalog/DS360c.pdf)
    33220A函數/任意波形產生器(https://www.keysight.com/tw/zh/assets/7018-01144/data-sheets/5988-8544.pdf)

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