簡易檢索 / 詳目顯示

研究生: 向國瑜
Siang, Guo-Yu
論文名稱: 鐵電氧化鉿鋯之負電容效應及類神經元件應用
Ferroelectric HfZrO2 for Negative Capacitance and Neuromorphic Device Applications
指導教授: 李敏鴻
Lee, Min-Hung
學位類別: 碩士
Master
系所名稱: 光電工程研究所
Graduate Institute of Electro-Optical Engineering
論文出版年: 2019
畢業學年度: 107
語文別: 中文
論文頁數: 74
中文關鍵詞: 鐵電材料氧化鉿鋯環繞式閘極場效電晶體深度學習
英文關鍵詞: Ferroelectric materials, HfZrO2, GAAFET, deep learning
DOI URL: http://doi.org/10.6345/NTNU201900910
論文種類: 學術論文
相關次數: 點閱:113下載:0
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • 鐵電材料的遲滯現象(Hysteresis)具有雙穩態的特性,滿足記憶體對於信號的存取要求和負電容特性(Negative capacitance, NC)電壓放大的概念,因此近年來對於鐵電材料進行廣泛的研究。由於負電容特性改善次臨界擺幅(subthreshold swing, SS),使MOSFET的SS在室溫下克服Boltzmann tyranny 2.3kbT/decade的物理極限,另一方面具有穩定遲滯現象和非破壞性讀取的特性適合作為非揮發性記憶體(Non-Volatile Memory, NVM)。
    本論文將針對鐵電材料氧化鉿鋯(HfZrO2, HZO)作為元件絕緣層的特性進行研究,首先將研究環繞式閘極場效電晶體搭載鐵電薄膜後,達到負電容效應,再來使用鐵電材料與非揮發性記憶體結合,研究應用於深度學習(Deep Learning, DL)且搭配不同結構與波型,尋找最佳的資料演算方式。

    Bi-stable state nature feature of hysteresis loops by ferroelectric materials satisfies the demands of storage signal purpose for memory and voltage amplification concept for negative capacitance. Therefore, it has been extensively investigated in recent years. Benefiting from negative capacitance effect, subthreshold swing (SS) demonstrated with improvement on to overcome the physical limitation of Boltzmann tyranny 2.3kbT/decade for MOSFET at room temperature. On the other hand, the property of hysteresis loops and non-destructive reading are suitable as Non-Volatile Memory (NVM).
    In this research, we will study the characteristics of ferroelectric material HZO as the dielectric layer of the device. Firstly, we will study the GAAFET and carry up the ferroelectric thin film HZO to achieve a negative capacitance effect, and then use ferroelectric materials in combination with NVM, and apply it to Deep Learning (DL) with different structures and waveforms to find the best data calculation method.

    Publication I 期刊論文 I 研討會論文 II 中文摘要 IV Abstract V 致謝 VI 目錄 VII 圖目錄 IX 表目錄 XIV 第1章 緒論 1 1-1 鐵電材料簡介 1 1-2 鐵電鉿鋯氧化物(Zr:HfO2)之特性分析 4 1-3 本論文架構 6 第2章 超陡峭次臨界擺幅之環繞式閘極奈米片場效電晶體 7 2-1 簡介 7 2-2 環繞式閘極奈米片場效電晶體之製作流程 8 2-3 環繞式閘極奈米片場效電晶體之電性結果 11 2-3-1 IDS-VGS之退火溫度 11 2-3-2 有無摻雜Zr之電性比較 13 2-3-3 深入研究退火900度特性與負電容效應 15 2-4 結果討論及分析 19 第3章 證明鐵電中負電容特性於暫態反應 21 3-1 簡介 21 3-2 量測機台設定及方式 23 3-2-1 量測機台介紹-Radiant 23 3-2-2 遲滯曲線之量測 24 3-2-3 量測機台介紹-Agilent B1530A 26 3-2-4 創建波型 29 3-3 MFIM (Metal-Ferroelectric-insulator-Metal)製作流程 40 3-4 實驗結果 42 3-5 結果討論與分析 47 第4章 鐵電記憶體於類神經元件應用 49 4-1 簡介 49 4-2 MFM (Metal-Ferroelectric-Metal)製作流程 51 4-2-1 MFM之TiN by ALD 51 4-2-2 MFM之TiN by PVD 52 4-3 仿生學習量測波行設定及方式 53 4-4 實驗結果 57 4-4-1 MFM之TiN by ALD 57 4-4-2 MFM之TiN by PVD 59 4-4-3 MFIM 61 4-5 結果討論與分析 63 第5章 總結與未來工作 67 5-1 總結 67 5-2 未來工作 67 參考資料 69

    [1] K. Ni, M. Jerry, J. A. Smith, and S. Datta, “A Circuit Compatible Accurate Compact Model for Ferroelectric-FETs, ” in Very Large Scale Integration (VLSI) Technology Symp., 2018, pp. 131-132.
    [2] T. Boescke, J. Heitmann, U. Schroder, “Integrated Circuit with Dielectric Layer, ” U.S. Patent 7 709 359 B2, May 4, 2010.
    [3] T. Mikolajick, S. Müller, T. Schenk, E. Yurchuk, S. Slesazeck, U. Schröder, S. Flachowsky, R. v. Bentum, S. Kolodinski, P. Polakowski and J. Müller, “Doped Hafnium Oxide-An Enable for Ferroelectric Field Effect Transistors, ’’ Aerospace Science and Technology, vol. 95, pp. 136-145, 2014.
    [4] T. S. Bösckea, J. Müllerb, D. Bräuhausc, U. Schröderd, and U. Böttgerc, “Ferroelectricity in Hafnium Oxide: CMOS Compatible Ferroelectric Field Effect Transistors, ” in International Electron Device Meeting (IEDM), 2011, pp. 547-550.
    [5] T. S. Böscke, St. Teichert, D. Bräuhaus, J. Müller, U. Schröder, U. Böttger and T. Mikolajick, “Phase Transitions in Ferroelectric Silicon Doped Hafnium Oxide, ’’ Applied Physics Letters, vol. 99, no. 11, pp. 112904, 2011.
    [6] J. Müller, T. S. Böscke, D. Bräuhaus, U. Schröder, U. Böttger, J. Sundqvist, P. Kücher, T. Mikolajick, and L. Frey, “Ferroelectric Zr0.5Hf0.5O2 Thin Films for Nonvolatile Memory Applications, ’’ Applied Physics Letters, vol. 99, iss. 11, pp. 112901, 2011.
    [7] J. Müller, U. Schröder, T. S. Böscke, I. Müller, U. Böttger, L. Wilde, J. Sundqvist, M. Lemberger, P. Kücher, T. Mikolajick, and L. Frey, “Ferroelectricity in Yttrium-doped Hafnium Oxide, ’’ Applied Physics Letters, vol. 110, no. 11, pp. 114113, 2011.
    [8] S. Müller, J. Müller, A. Singh1, S. Riedel, J. Sundqvist, U. Schroeder and T. Mikolajick, “Incipient Ferroelectricity in Al-Doped HfO2 Thin Films, ’’ Advanced Functional Materials, vol. 22, no. 11, pp. 2412-2417, June 6, 2012.
    [9] T. Schenk, S. Mueller, U. Schroeder, R. Materlik, A. Kersch, M. Popovici, C. Adelmann, S. V. Elshocht and T. Mikolajick, “Strontium Doped Hafnium Oxide Thin Films: Wide Process Window for Ferroelectric Memories. ” ESSDC., 2013. 6818868 .
    [10] A. G. Chernikova, D. S. Kuzmichev, D. V. Negrov, M. G. Kozodaev, S. N. Polyakov, and A. M. Markeev., “Ferroelectric Properties of Full Plasma-Enhanced ALD TiN/La:HfO2/TiN Stacks, ” Applied Physics Letters, vol. 108, no. 24, pp. 242905, 2016.
    [11] S. Müller, H. Mulaosmanovic, S. Slesazeck, J. Müller, and T. Mikolajick, “CMOS Compatible Ferroelectric Devices for Beyond 1X nm Technology Nodes, ” in Solid State Device and Materials(SSDM), 2017, pp. 539-540.
    [12] T. S. Bösckea, J. Müllerb, D. Bräuhausc, U. Schröderd, and U. Böttgerc, “Ferroelectricity in Hafnium Oxide: CMOS Compatible Ferroelectric Field Effect Transistors, ” in International Electron Device Meeting (IEDM), 2011, pp. 547-550.
    [13] P. Polakowski, S. Riedel, W. Weinreich, M. Rudolf, J. Sundqvist, K. Seidel, and J. Müller, “Ferroelectric Deep Trench Capacitors based on Al:HfO2 for 3D Nonvolatile Memory Applications, ” in International Memory Workshop (IMW), 2014, pp. 1-4.
    [14] C. H. Cheng and A. Chin, “Low-Leakage-Current DRAM-Like Memory Using a One-Transistor Ferroelectric MOSFET With a Hf-Based Gate Dielectric, ” Electron Device Letter, vol. 35, pp. 138-140, 2014.
    [15] C. H. Cheng and A. Chin, “Low-Voltage Steep Turn-on PMOSFET Using Ferroelectric High-k Gate Dielectric, ” IEEE Electron Device Letter, vol. 35, pp. 274-276, 2014.
    [16] M. H. Park, H. J. Kim, Y. J. Kim, T. Moon,K. D. Kim, and C. S. Hwangn, “Toward a Multifunctional Monolithic Device Based on Pyroelectricity and the Electrocaloric Effect of Thin Antiferroelectric HfxZr1-xO2 Films, ” Nano Energy, vol. 12, pp. 131-140, 2015.
    [17] Y. C. Chiu, C. H. Cheng, C. Y. Chang, M. H. Lee, H. H. Hsuand, and S. S. Yen, “Low Power 1T DRAM/NVM Versatile Memory Featuring Steep Sub-60-mV/decade Operation, Fast 20-ns Speed, and Robust 85oC-Extrapolated 1016 Endurance, ” in Very Large Scale Integration (VLSI) Technology Symp., 2015, pp. 184-185.
    [18] S. Fujii, Y. Kamimuta, T. Ino, Y. Nakasaki, R. Takaishi, and M. Saitoh, “First Demonstration and Performance Improvement of Ferroelectric HfO2-Based Resistive Switch With Low Operation Current and Intrinsic Diode Property, ” in Very Large Scale Integration (VLSI) Technology Symp., 2016, pp. 978-979.
    [19] H. Mulaosmanovic, J. Ocker, S. Müller, M. Noack, J. Müller, P. Polakowski, T. Mikolajick, and S. Slesazeck, “Novel Ferroelectric FET based Synapse for Neuromorphic Systems, ” in Very Large Scale Integration (VLSI) Technology Symp., 2017, pp. 176-177.
    [20] R. Eskandari, X. Zhang, and L. M. Malkinski, “Polarization-Dependent Photovoltaic Effect in Ferroelectric-Semiconductor System, ” Applied Physics Letters, vol. 110, pp. 121105, 2017.
    [21] M. Dragoman, M. Aldrigo, M. Modreanu, and D. Dragoman, “Extraordinary Tunability of High-Frequency Devices Using Hf0.3Zr0.7O2 Ferroelectric at Very Low Applied Voltages, ” Applied Physics Letters, vol. 110, pp. 103104, 2017.
    [22] J. V. Houdt, “Memory Technology for the Terabit Era: from 2D to 3D, ” in Very Large Scale Integration (VLSI) Technology Symp., 2017, pp. 978-979.
    [23] S. W. Smith, A. R. Kitahara, M. A. Rodriguez, M. D. Henry, and M. T. Brumbach, and J. F. Ihlefeld, “Pyroelectric Response in Crystalline Hafnium Zirconium Oxide (Hf1-xZrxO2) Thin Films, ” Applied Physics Letters, vol. 110, pp. 072901, 2017.
    [24] F. Huang, Y. Wang, X. Liang, J. Qin, Y. Zhang, X. Yuan, Z. Wang, B. Peng,L. Deng, and Q. Liu, “HfO2-Based Highly Stable Radiation-Immune Ferroelectric Memory, ” IEEE Electron Device Letter, vol. 38, pp. 330-333, 2017.
    [25] A. Chen, “Nanoelectronic Device Research for beyond - CMOS Technologies, ” in “Emerging Technologies for the post 14nm Node Area, ” in International Electron Device Meeting (IEDM) short course, Dec. 8, 2012.
    [26] J. Müller, T. S. Böscke, D. Bräuhaus, U. Schröder, U. Böttger, J. Sundqvist, P. Kücher, T. Mikolajick, and L. Frey, “Ferroelectric Zr0.5Hf0.5O2 Thin Films for Nonvolatile Memory Applications, ’’ Applied Physics Letters, vol. 99, iss. 11, pp. 112901, 2011.
    [27] M. A. Karim, Sriramkumar Venugopalan, Yogesh Singh Chauhanm Darse Lu, Ali Niknejad, and Chenming Hu, “Drain Induced Barrier Lowering (DIBL) Effect on the Intrinsic Capacitances of Nano-Scale MOSFETs, ” in Nano Science and Technology Institute (NSTI)-Nanotech, vol. 2, pp. 814-817, 2011.
    [28] S. Salahuddin, and S. Datta, “Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices, ” Nano Letters, vol. 8, no. 2, pp. 405-410, 2008.
    [29] P. Sharma, K. Tapily, A. K. Saha, J. Zhang, A. Shaughnessy, A. Aziz, G.L. Snider, S. Gupta, R. D. Clark, S. Datta, “Impact of Total and Partial Dipole Switching on the Switching Slope of Gate-Last Negative Capacitance FETs with Ferroelectric Hafnium Zirconium Oxide Gate Stack, ” in Very Large Scale Integration (VLSI) Technology Symp., 2017, pp. 154-155.
    [30] W. Chung, M. Si, P. R. Shrestha, J. P. Campbell, K. P. Cheung, and P. D. Ye, “First Direct Experimental Studies of Hf0.5Zr0.5O2 Ferroelectric Polarization Switching Down to 100-picosecond in Sub-60mV/dec Germanium Ferroelectric Nanowire FETs, ” in Very Large Scale Integration (VLSI) Technology Symp., 2018, pp. 89-90.
    [31] C. J. Su, T. C. Hong, Y. C. Tsou, F. J. Hou, P. J. Sung, M. S. Yeh, C. C. Wan, K. H. Kao, Y. T. Tang, C. H. Chiu, C. J. Wang, S. T. Chung, T. Y. You, Y. C. Huang, C. T. Wu, K. L. Lin, G. L. Luo, K. P. Huang, Y. J. Lee, T. S. Chao, W. F. Wu, G. W. Huang, J. M. Shieh, W. K. Yeh, and Y. H. Wang, “Ge Nanowire FETs with HfZrOx Ferroelectric Gate Stack Exhibiting SS of Sub-60 mV/dec and Biasing Effects on Ferroeleclectric Reliability, ” in International Electron Device Meeting (IEDM) Tech. Dig., 2017, pp. 369-372.
    [32] S. Salahuddin, and S. Datta, “Can the Subthreshold Swing in a Classical FET be Lowered Below 60 mV/decade, ” in International Electron Device Meeting (IEDM) Tech. Dig., 2008, pp. 693-696.
    [33] M. H. Lee, J.-C. Lin, and C.-Y. Kao, “Hetero-Tunnel Field-Effect-Transistors with Epitaxially Grown Germanium on Silicon, ” IEEE Trans. on Electron Device, vol. 60, no.7, pp. 2423-2427, 2013.
    [34] M. Hoffmann, B. Max, T. Mittmann, U. Schroeder, S. Slesazeck, and T. Mikolajick, NaMLab gGmbH, Noethnitzer Str, “Demonstration of High-speed Hysteresis-free Negative Capacitance in Ferroelectric Hf0.5Zr0.5O2, ” in International Electron Device Meeting (IEDM) Tech. Dig., 2018, pp. 727-730.
    [35] M. Hoffmann, Franz P. G. Fengler, M. Herzig, T. Mittmann, B. Max, U. Schroeder, R. Negrea, P. Lucian, S. Slesazeck and T. Mikolajick, “Unveiling the Double-Well Energy Landscape in a Ferroelectric Layer, ” Nano Letters, vol. 565, pp. 463-467, 2019.
    [36] Premier II Ferroelectric Test System Brochure, pp. 1-2.
    [37] B1500A Semiconductor Device Analyzer user’s manual, pp. 1,4-2,32.
    [38] Agilent B1530A Waveform Generator/Fast Measurement Unit, pp. 1,5-2,12.
    [39] Y. C. Chiu, Y.-C. Chiu, C.-H. Cheng, C.-Y. Chang, M.-H. Lee, H.-H. Hsu, and S.-S. Yen, “Low Power 1T DRAM/NVM Versatile Memory Featuring Steep Sub-60-mV/decade Operation, Fast 20-ns Speed, and Robust 85°C-Extrapolated 1016 Endurance, ” in Very Large Scale Integration (VLSI) Technology Symp., 2017, pp. 184-185.
    [40] A. I. Khan, K. Chatterjee, B. Wang, S. Drapcho, L. You, C. Serrao, S. R. Bakaul, R. Ramesh, and S. Salahuddin, “Negative Capacitance in a Ferroelectric Capacitor, ” Nature Materials 14, pp. 182-186 , 2015.
    [41] A. I. Khan, M. Hoffmann, K. Chatterjee, Z. Lu, R. Xu, C. Serrao, S. Smith, L. W. Martin, C. Hu, R. Ramesh, and S. Salahuddin, “Differential Voltage Amplification from Ferroelectric Negative Capacitance, ” Applied Physics Letters, vol. 111, pp. 253501, 2017.
    [42] M. Hoffmann, A. I. Khan, C. Serrao, Z. Li, S. Salahuddin, M. Pešić, S. Slesazeck, U. Schroeder, and T. Mikolajick, “Ferroelectric Negative Capacitance Domain Dynamics, ” Applied Physics Letters, vol. 123, pp. 184101 ,2018.
    [43] Y. J. Kim, H. Yamada, T. Moon, Y. J. Kwon, C. H. An, H. J. Kim, Y. H. Lee, S. D. Hyun, M. H. Park, and C. S. Hwang, “Time-Dependent Negative Capcitance Effects in Al2O3/BaTiO3 Bilayers, ” Nano Letters, vol. 16, pp. 4375-4381, 2016.
    [44] M. Jerry, P.-Y. Chen, J. Zhang, P. Sharma, K. Ni, S. Yu, and S. Datta, “Ferroelectric FET Analog Synapse for Acceleration of Deep Neural Network Training, ” in International Electron Device Meeting (IEDM) Tech., 2017, pp. 140-142.
    [45] K. Ni, M. Jerry, J. A. Smith, and S. Datta, “A Circuit Compatible Accurate Compact Model for Ferroelectric-FETs, ” in Very Large Scale Integration (VLSI) Technology Symp., 2018, pp. 131-132.
    [46] J. Woo, K. Moon, J. Song, S. Lee, M. Kwak, J. Park, and H. Hwang, “Improved Synaptic Behavior Under Identical Pulses Using AlOx/HfO2 Bilayer RRAM Array for Neuromorphic Systems, ” IEEE Electron Device Letter, vol. 37, no. 8, pp. 994-997, 2016.
    [47] L. Gao, I. T. Wang, P. Y. Chen, S. Vrudhula, J. S. Seo, Y. Cao, T. H. Hou, and S. Yu, “Fully Parallel Write/Read in Resistive Synaptic Array for Accelerating on-Chip Learning, ” Nanotechnology, vol. 26, no. 45, pp. 455204, 2015.
    [48] S. Park, A. Sheri, J. Kim, J. Noh, J. Jang, M. Jeon, B. Lee, B. H. Lee, and H. Hwang, “Neuromorphic Speech Systems Using Advanced ReRAM-Based Synapse, ” in International Electron Device Meeting (IEDM) Tech., 2013, pp. 625-628.
    [49] S. H. Jo, T. Chang, I. Ebong, B. B. Bhadviya, P. Mazumder, and W. Lu, “Nanoscale Memristor Device as Synapse in Neuromorphic Systems, ” Nano Letters, vol. 10, no. 4, pp. 1297-1301, 2010.
    [50] M. H. Lee, K.-T. Chen, C.-Y. Liao, S.-S. Gu, G.-Y. Siang, Y.-C. Chou, H.-Y. Chen, J. Le, R.-C. Hong, Z.-Y. Wang, S.-Y. Chen, P.-G. Chen, M. Tang, Y.-D. Lin, H.-Y. Lee, K.-S. Li, and C. W. Liu, “Extremely Steep Switch of Negative-Capacitance Nanosheet GAA-FETs and FinFETs, ” Technical Digest, International Electron Device Meeting (IEDM), 2018, pp. 735-738.
    [51] S. Oh, T. Kim, M. Kwak, J. Song, J. Woo, S. Jeon, I. K. Yoo, and H. Hwang, “HfZrOx-Based Ferroelectric Synapse Device With 32 Levels of Conductance States for Neuromorphic Applications, ” IEEE Electron Device Letter, vol. 38, pp. 732-735, 2017.

    無法下載圖示 本全文未授權公開
    QR CODE