隨著製程技術的進步，晶片佈局面積得以縮小，這也意味著電路可在操作在更低的電壓。智能穿戴產品和物聯網市場的快速增長，如何最大限度地降低功耗已成為關鍵的設計要求。強調低功耗使產品更具有競爭力。因為逐次逼近型模數轉換器結構簡單，只需要一個比較器。大部分電路由數字邏輯電路組成，數據轉換所需的功耗隨著製程提升而降低。因此，元件較少且低功耗的逐次逼近式類比數位轉換器備受重視。

藉由新增額外的電容，並配合使用浮動式電容開關切換技術，使得整體電路之電容、功率以及面積大幅下降。本論文所實現之架構相較於傳統十位元之類比數位轉換器約可減少62.5%的電容使用值，並降低94.93%的能量消耗。另外，在供應電源為1.2-V的操作下，本研究採用TSMC 180nm 1P6M的製程，取樣頻率1MHz，輸入頻率為198.517kHz，可得訊號雜訊失真比58.22dB，DNL與INL分別為+0.4 LSB/-0.8 LSB及+0.8LSB/-0.8LSB，總消耗功率為48.9μW，品質因數FOM為73.456 -fJ/conversion-step。

With the advancement of process technology, the chip layout area has been reduced, which also means that the circuit can be operated at a lower voltage. Minimizing power consumption has become the key design requirement with the recent rapid growth of the Internet of Things (IoT) market and smart wearable products. Low power is emphasized to make the circuit applicable to it be competitive. Due to the simple structure of the successive approximation analog-to-digital converter, only one comparator is needed. Most of the circuits are composed of digital logic circuits, and the power consumption required for data conversion decreases as the manufacturing process improves. Therefore, successive approximation analog-to-digital converters with fewer components and low power consumption are highly valued.
In this paper, by adding additional capacitors and using floating capacitor switching technology, the capacitance, power, and area of the overall circuit are greatly reduced. Compared with the traditional 10-bit analog-to-digital converter, the architecture implemented in this paper can reduce the capacitor usage value by 62.5% and reduce the energy consumption by 94.93%. In addition, under the operation of 1.2-V power supply, this research adopts the TSMC 180nm 1P6M process, the sampling frequency is 1MHz, the input frequency is 198.517kHz, and the signal-to-noise-distortion ratio is 58.22dB, and the DNL and INL are +0.4 LSB /-0.8 LSB and +0.8LSB/-0.8LSB, the total power consumption is 48.9μW, and the quality factor FOM is 73.456 -fJ/conversion-step.

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