本論文主要研究應用在高速電路之靜電放電防護設計，所有測試電路皆在CMOS製程中完成設計，透過分散式電路設計與低電容防護元件的組合，達到不影響高速性能並提供有效靜電放電防護的效果，並與傳統既有之二極體與矽控整流器做比較。
在本論文中，提出了一款新型的電源線觸發之矽控整流器 (PLTSCR)，π-PLTSCR可以不用透過電源線間靜電放電箝制電路 (power-rail ESD clamp circuit) 便能夠達成四個模式 (PS, PD, NS, and ND) 的靜電排放。由於無需使用電源線間靜電放電箝制電路，電路的面積便可以節省45%。本次提出的新型設計，除了可以應用在高速電路的防護，並且還可以省下更多的成本。
最後，為了驗證防護電路是否可以真正保護內部電路，本論文使用轉阻放大器 (Trans-impedance amplifier, TIA)，作為被保護的內部電路，分別搭配π-diode、π-SDSCR、π-RTSCR以及π-PLTSCR進行防護，並且進行高頻量測與靜電耐受度量測，確認防護電路的功能是否正常以及其對轉阻放大器的性能影響。透過實驗結果可知，創新設計可以提供給TIA電路6kV的靜電耐受度，且造成的增益下降大約為1dB，並未對性能造成過大影響。

This paper mainly studies the design of electrostatic discharge protection applied in high-speed circuits. All test circuits are designed in CMOS process. Through the combination of distributed circuit design and low-capacitance protective elements, it achieves effective electrostatic discharge protection without affecting high-speed performance, and is compared with traditional diodes and silicon-controlled rectifiers.
In this paper, a new type of power line-triggered silicon-controlled rectifier (PLTSCR) is proposed. The π-PLTSCR can achieve electrostatic discharge in four modes (PS, PD, NS, and ND) . The circuit area can be saved by 45%. This new design can not only be applied to the protection of high-speed circuits but also can save more costs.
Finally, in order to verify whether the protective circuit can truly protect the internal circuit, this paper uses a trans-impedance amplifier (TIA) as the protected internal circuit and performs high-frequency measurement and electrostatic tolerance measurement to confirm whether the protective circuit is functioning normally and its impact on the performance. Through the experimental results, it is found that does not have a significant impact on the performance.

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