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研究生: 林健群
LIN, CHIEN-CHUN
論文名稱: 積體電路在嚴苛環境下的靜電放電研究
ESD Research of Integrated Circuits under Harsh Environment
指導教授: 林群祐
Lin, Chun-Yu
口試委員: 彭盛裕
Peng, Sheng-Yu
蔡銘憲
Tsai, Ming-Hsien
林群祐
Lin, Chun-Yu
口試日期: 2023/04/27
學位類別: 碩士
Master
系所名稱: 電機工程學系
Department of Electrical Engineering
論文出版年: 2023
畢業學年度: 111
語文別: 英文
論文頁數: 91
中文關鍵詞: 靜電放電系統層級的靜電放電環境的溫度環境的相對濕度
英文關鍵詞: electrostatic discharge (ESD), system-level ESD, ambient temperature, ambient relative humidity
研究方法: 實驗設計法
DOI URL: http://doi.org/10.6345/NTNU202300591
論文種類: 學術論文
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  • 本論文旨在研究不同尺寸之靜電放電防護元件及各種靜電放電防護電路受到環境因子影響,而導致之靜電放電防護能力變化。現今系統單晶片技術的蓬勃發展,在IC系統廠將一整個電子系統整合到單一晶片的IC中,因此單一顆晶片即為一個系統。在晶圓代工廠製造IC後,需要通過元件層級的靜電放電測試來確保IC元件的可靠度,而在系統組裝成產品到消費者手中,需要通過系統層級的靜電放電測試標準 (IEC 61000-4-2) 來確保產品在較潮濕或炎熱的地區不會影響消費者的體驗,因此本研究採用系統層級的靜電槍來進行實測,實測待測物在高濕及高溫環境下的靜電放電耐受度。在論文第二章以矽控整流器 (SCR) 作為靜電放電防護元件來測試環境相對濕度對待測物之影響。在論文第三章則以輸出級的靜電放電防護電路來測試環境溫度對其之影響,待測物為電源端到地的靜電放電防護電路。
    依據本論文第二章及第三章的量測結果,在高溫環境下,待測物的電荷載流子遷移率會隨溫度上升而增加,當靜電槍接觸到待測物時,靜電放電會對其造成嚴重損害。在高濕環境下,待測物表面會形成一層水,這層水的表面張力會縮短靜電槍和待測物的非接觸放電距離,導致待測物的靜電放電耐受度下降。本研究對於日後需要了解環境溫度及環境相對濕度對IC之影響有所幫助。

    This thesis is to study the effect of environmental factors on the different sizes of electrostatic discharge (ESD) protection components and various ESD protection circuits. Environmental factors will cause changes in ESD protection ability. With the rapid development of system-on-chip (SOC) technology, an entire electronic system is integrated into a single chip in an integrated circuit (IC) system factory. Thus, a single chip is a system. It is necessary to pass the component-level ESD test to ensure the reliability of the component after the chip is manufactured in the wafer foundry. The system is assembled into a product before delivering to the consumer. It needs to pass the system-level ESD test. The system-level ESD test standard, IEC 61000-4-2, ensures that the product does not affect the consumer experience in high humidity or hot regions. Therefore, this study uses a system-level electrostatic gun (ESD gun) for an actual measurement. The test is to measure the ESD robustness of the devices under test (DUT) under a high humidity and high temperature environment. Chapter 2 uses the silicon-controlled rectifiers (SCR) as ESD protection components to test the effects of ESD robustness under ambient relative humidity. In Chapter 3, the ESD protection circuit of the output stage is used to test the effects of ESD robustness under the ambient temperature. The DUT is the ESD protection circuit from the power supply (VDD) to the ground (VSS).
    According to the measurement results in Chapter 2 and Chapter 3, the charge carrier mobility of the DUT will increase with the temperature rise under the high ambient temperature. The ESD current will cause severe damage to it when the ESD gun contacts the DUT. A layer of water will form on the surface of the DUT under the high ambient relative humidity. The surface tension of this layer of water will shorten the air discharge distance between the ESD gun and the DUT to a certain extent. A shorter air discharge distance will lead to a decrease in the ESD robustness of the DUT. This study will help in understanding the effects of ambient temperature and ambient relative humidity on ICs.

    Chapter 1 Introduction 1 1.1 Background of ESD 1 1.2 ESD Test Standards 2 1.3 Background of ESD Protection Circuits 4 1.4 Literature Review 9 1.4.1 IC Reliability under Harsh Environment 9 1.4.2 Experimental Environment under High Relative Humidity 11 1.4.3 Effect of High Relative Humidity on Discharge Voltage 12 1.4.4 Effect of Widened Air Gap on Discharge Voltage 13 1.5 Research Motivation 13 1.6 Thesis Organization 14 Chapter 2 On-Chip ESD Protection Component under Harsh Environment 15 2.1 Typical Design of On-Chip ESD Protection Component 15 2.2 Component Parameters 17 2.3 Experimental Environment 18 2.4 Measured Results of ESD Protection Component 23 2.4.1 Measured TLP I-V Characteristic 23 2.4.2 Measured HBM Results 24 2.4.3 Measurement Results under System-Level ESD Test 25 2.4.4 Comparison of Test Devices under Environment Change Conditions 33 2.4.5 Comparison of Test Devices under Component-Level and System-Level ESD Tests 36 2.5 Summary 37 Chapter 3 On-Chip ESD Protection Circuits under Harsh Environment 38 3.1 Applications of Output Stage 38 3.2 Design of Stacked Output Stage 41 3.3 On-Chip ESD Protection Circuits for Output Stage 44 3.4 Component Parameters of Output Stage with ESD Protection Circuits 49 3.5 Measured Results of Output Stage with ESD Protection Circuits 53 3.5.1 Measured Transient Waveforms 53 3.5.2 Measured TLP I-V Characteristic 54 3.5.3 Measured HBM Results 57 3.5.4 Measurement Results under System-Level ESD Test 57 3.5.5 Comparison of Test Circuits under Environment Change Conditions 79 3.5.6 Comparison of Test Circuits under Component-Level and System-Level ESD Tests 82 3.6 Summary 83 Chapter 4 Conclusion and Future Work 84 4.1 Conclusion 84 4.2 Future Work 85 References 86 Vita 90 Publication List 91

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