高等加密標準(Advanced Encryption Standard, AES)硬體實現在現場可程式化閘陣列(FPGA)與特殊用途積體電路(ASIC)已經被很廣泛的討論；然而在嵌入式硬體的應用上，低產率與小面積的設計在近幾年也開始被研究。
　　本研究提出一個小面積的硬體電路，採用8位元的架構來實現AES-128的規格，其中使用Block RAM來完成位元組替換(SubByte)與移列轉換(ShiftRow)的動作，使用共用電路方式製作混行轉換(MixColumns)；以軟體來取代硬體的金鑰擴展(KeyExpansion)，來節省電路面積。透過上述所提出的方式在FPGA上所完成的實驗數據，其資源消耗為109個Slice、速度可達到94.056Mhz，是在目前文獻中8位元架構中最快的設計。
　　並且針對實現影像加解密的應用時所遇到的問題，本研究分別以各文獻中的方法實做，並且針對其各種不同的結果做分析，對於他們的缺點加以改良，優點予以保留，整理出一個更好的加密工作模式。

Advance Encryption Standard (AES) hardware implementation in FPGA and ASIC have been intensely discussed. However, lower throughput and area designs have also been investigated in the recent years for embedded hardware applications.
　　This paper presents an 8-bit AES implementation with a speed of 94.056MHz and low area of 109 slices, which is the faster 8-bit AES design among literature reports. There is a built-in Block RAM for SubByte and ShiftRow, KeyExpansion utilizing software instead of hardware.
　　In order to solve the problems encountered during the image encryption and decryption, this thesis tests methods from other reports, analyses results stemming therefrom, The final goal of this thesis is to improve their shortcomings and preserve their strengths, so as to come up with a better encryption and decryption operation mode.

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