針對未來 sub-10nm 發展，節能電晶體將是決勝關鍵，低次臨界擺幅電
晶體發展關係到 V dd 降低之節能發展，而負電容觀念為其中一種可能，於
2008 年由 UC Berkeley 的 S. Salahuddin 教授所揭露負電容觀念有助於 body
factor 小於 1，利用結晶的鐵電介電質得到負電容，以 PZT/STO 材料模擬增
強電容的作用也被提出，EPFL 進而使用 P(VDF-TrFE)材料於實驗上展現成
果，負電容閘極堆疊俱有內部電壓放大的效果。
本研究的目標就是發展利用鐵電負電容，達到低次臨界擺幅次世代電
晶體研究，目前發表的負電容論文所使用的鐵電材料多是用鋯鈦酸鉛(PZT)、
鉭酸鍶鉍(SBT)、鈦酸鍶(STO)…，這些材料由於與矽的熱力學上不相容，
且這些材料部分元素具有毒性汙染，並會造成 MOSFET 製程不相容，故於
此計劃將發展 oxide-based，如 HfO 2 , HfO 2 :Si, HfO 2 :Zr，也都有機會造成極
化效果，及反鐵電效果達到 MOSCAP 時有負電容效應，目標則是改善次臨
界擺幅(subthreshold swing)，探討其中物理，故具實用性及新穎性。並予以
模擬手法，將理論觀點導入並尋求超陡峭電晶體的可能，故俱獨特性。

For the development of sub-10nm technology node, the devices with
energy conservation and carbon reduction is necessary. The steep subthreshold
swing FET may be the solution with lowing V dd , and negative capacitance
concept is a candidate for this requirement. Prof. S. Salahuddin, UC Berkeley,
has disclosed the concept of negative capacitance for body factor < 1 in 2008.
They reported the metastable of Gibbs free energy to obtain negative
capacitance effect, and simulated by PZT/STO. EPFL also experimented to
demonstrated the negative capacitance concept with P(VDF-TrFE) and reported
the voltage amplification.
In this project, we will develop the low swing FET by negative capacitance concept. We
will develop it on MOS-base line platform for sub-10nm technology node. We will make
effort in the development the ferroelectric oxide-based dielectric MOSFET. The reports
disclosed the FE material are PZT, SBT, STO…etc. with lots of issues such as, process
incompatible, toxic…etc. Therefore, the oxide-based with ferroelectric negative capacitance is
necessary, such as HfO 2 , HfO2:Si, HfO 2 :Zr. The NC with AFE is the approach and discuss the
physics for the practicability and novelty. We also including the simulation and modeling to
predict the high performance selector structure. It is uniqueness.

53

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