本論文研究的目的在於設計並合成出可以植入於腦部內的植入式多通道棘波分類電路，提出的電路架構能夠處理多通道的腦波資料，所支援的功能包含棘波偵測、特徵擷取以及棘波分類，並具有低面積、低功耗的優勢以及良好的分類效果。根據植入生物體內的需求，電路的面積及功耗都是需要著重考量的部分，因為完成後的晶片會接觸到大腦，面積如果過大會壓迫到腦部，而功耗如果太高會導致晶片溫度過高而傷害到大腦，造成腦神經或是細胞組織受損。

本研究所提出的架構是基於NEO演算法則做為棘波偵測器和Peak Detection and Area Computation(PDAC)演算法做為特徵擷取器，並使用非監督式學習演算法Competitive Learning透過特徵資料做學習，學習完之後交給Nearest Neighbor Classifier做棘波分類使用。在架構設計上透過運算單元的共享，並將64通道的棘波分類系統電路架構於ASIC Flow上實作，使用90nm製程做電路的實現，並於電路設計中導入Clock Gating技術來降低電路動態功耗，完成低面積、低功耗的多通道棘波分類電路。

最後於論文後方與其他現有的架構做比較，證明以競爭性學習法則為基礎的棘波分類系統有著良好的面積及功耗表現，且具有不錯的分類效果。

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